In power electronics, when we build the important circuits like Totem pole PFC circuit or Quadrant VII converters etc, how do we start looking into parasitic elements (inductance and capacitances ) and do the calculations or simulations at specified frequencies.

  • \$\begingroup\$ Check out LTSpice. \$\endgroup\$ – DKNguyen Apr 8 at 20:32

how do we start looking into parasitic elements

This is something you learn by experience.

Like, how to apply Ohm's Law to life. ;)

We learn on the job, or from simulators like Saturn PCB.exe, that geometry is the key factor.

  • For conductors that are straight, the inductance of a short wire with a length/width ratio,

  • l/w = 6:1, L = 0.5 nH/mm = 5 nH/cm and

  • l/w = 80 or 1.0 nH/mm = 10 nH/cm and
  • for parastics we call it "effect series inductance" = ESL and for dielectrics they all have an "effective series resitance"= ESR
  • we discover that Murata makes low ESL RF SMD caps that l/w=1:2 instead of 2:1 ratio like 402's, 603's, 1206's

    • For Diodes some learn as I have that C_diode = k/Pd meaning the 0V bias capacitance increases with power rating from bulk size for some figure of merit k
    • but material like SiC or Si or GaAs or Si- metalized terminals of Schottky diodes can reduce the internal series resistance , Rs
    • and for all diodes the Pd rating * Rs is somewhat constant in the same materials of different sizes meaning the incremental resistance reduces and junction capacitance rises with increasing diode sizes.

      • this is why CMOS ESD diodes can only handle 5mA DC yet are faster than the CMOS they are protecting from Latchup failures. if they were too slow, how could they protect CMOS?
    • you learn how to calibrate your fingers tips in pF with a 1mm gap or nF with pressure.

    • you learn what is the capacitance of a trace over a ground plane by the geometry of trace width to dielectric thickness in pF/mm
    • the same is true for twisted pair being around 100pF/m with some standard dielectric thickness and that the twisted pair impedance is \$Z_o=\sqrt{ \dfrac{L}{C}}\$
    • just as it is for parasitic PCB traces with ESL and C to ground plane to make a controlled impedance strip line. this but increasing can increase thermal noise.
  • you learn how to deal with MOSFET Q charge and Ciss, Coss which occurs due to Vgs threshold crossing the Ohmic boundary and that Q*RdsOn is somewhat constant or is affected by design, quality and cost or Vds rating.

Typically the parasitic values can be found from the manufacturer in a datasheet or product document.

For example murata has frequency graphs that show the parasitics in capacitors and inductors they manufacture which relate to the Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL)
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After they parastics are known they can be simulated or factored into equations to predict how the DC to DC circuit will perform.


You can also include coupling between one trace and another trace, by electric fields. Whether wires or traces, for spacings about the same as the width of wires or traces, just use the parallel-plate capacitor equation for a useful estimate

C = E0 * Er * Area/Distance

To use this, you need to know the impedance of the circuit at the frequency of interest.


Also consider including magnetic coupling, from a wire to some loop. High speed switching of currents is a huge problem, even for the regulation circuits of those same switching regulators. And microcontroller clocks or output pins are a problem if near a sensitive analog (and crystal oscillators are sensitive analog circuits) circuits.

V = 1e-7 * Area/Distance * dI/dt

A wire carrying a current that switches 100 amps in 100 nanoSeconds (1e+9 amps/sec) and located 0.1 meter away from a 0.1meter by 0.1 meter loop on your PCB, will have (this equation ignores the fully accurate equation, which includes a natural-log)

V = 2e-7 * 0.1m * 0.1m /0.1m * 1e+9

V = 2e-7 *0.1 * 1e+9 = 2e(-7-1+9) = 2e+1 = TWENTY VOLTS


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