0
\$\begingroup\$

I'm trying to implement a 64 bit FIFO Data Buffer in Verilog. My design allows for data to be written at 4 bytes or 1 byte at a time, and I'm simply using two multiplexers with control signals for determining which mode it is writing to a memory array. Before the data is written to the memory array, does it need to be passed into a register or can it just be directly inputted into the memory array at wherever the write point is currently?

\$\endgroup\$
1
\$\begingroup\$

In FIFO implementations it's always the read(capture) & write(launch) pointers that need to be registered.

Refer this link

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.