I'm trying to implement a 64 bit FIFO Data Buffer in Verilog. My design allows for data to be written at 4 bytes or 1 byte at a time, and I'm simply using two multiplexers with control signals for determining which mode it is writing to a memory array. Before the data is written to the memory array, does it need to be passed into a register or can it just be directly inputted into the memory array at wherever the write point is currently?
In FIFO implementations it's always the read(capture) & write(launch) pointers that need to be registered.
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