Calculating voltage drop and current use of an IC

Question

I’m trying to figure out the voltage drop and the current used by a Johnson counter from a data sheet and am feeling a little lost.

In particular I’m looking at a CD4022B from TI.

I’m looking at the static electrical characteristics on page 3. I’m getting confused as to the relationship between Vo, Vin, and Vdd.

In hooking up the IC I’m assuming Vss is the input voltage, Vdd is the GND, and Vout is what is outputted through the decoded outputs (0-9).

I’m also a little lost on the different output and input states listed. I’m assuming the Output High (source) current Ioh is referring to when one of the decoded outputs is high, and that the Output Low (sink) current Iol is referring to current draw by the IC when the decoded outputs are low.

I’m also assuming right now that Vol are also referencing the decoded outputs, and Vil is referencing Vss, but I’m guessing that assumption is wrong simply based on what the numbers are.

Any help would be great in figuring this out. Thanks.

Answer 1

Vdd is the power supply voltage.

Vin is the signal input voltage, and Vout is the signal output voltage.

Ioh and Iol are the currents that an output pin can sink or source. They are not directly related to the current the chip draws from the power supply.

Vih is the minimum input voltage that will be recognised as a logic High

Vil is the maximum input voltage that will be recognised as a logic Low.

Vol and Voh are the maximum and minimum output voltages for Low and High logic levels at the specified output currents.

Answer 2

Perhaps this fills in the gaps to your knowledge of standard CMOS datasheets.

Generally CD4xxx series was high voltage and high impedance. > 300 ~ 1000 Ohm for RdsOn . Since both Nch Pch drivers conduct during transition they must be high impedance to reduce current spike between V+ = Vdd (drain) and V- = Vss (source).

Looking at all the dozen or so of CMOS families as they became faster, they limited Vdd max to use lower RdsOn which raises the current and thus speed from dV/dt=Ic/C from [pF] loads ( Miller cap and traces above ground plane)

As Logic families have migrated to lover voltages, they must also lower RdsOn ( which is a "cross-conduction condition).

This is why every CMOS IC needs a 0.01uF decoupling cap while TTL was every 10 IC's as transition current spikes are normal, limited by Rs and depends on number of similar CMOS inside are switching at same time.

From the Recommended Operating Conditions Tables

• for 74LVxxx family is rated 2V to 5.5V
• worst case 5V, - 10% =
  • at Vdd=4.5V Vol = 0.55V max @ Iol=12mA
  • thus output resistance is Vol/Iol = 550 mV/12 mV= 46 Ω (min.) (ref SN74LV393A)
  • this is how you can interpret CMOS drivers when loaded by some know resistance or capacitive loads for risetime or voltage shift from the rails.