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I've got a circuit that I am simulating to help understand how a latch-up prevention circuit that is being used in a design works. The circuit: enter image description here

My question: As i increase the DC voltage V3 at the -ve terminal the voltage at the +ve terminal also increases without any feedback loop. Could someone please explain this? Eg. V3 at 4V increases the +ve voltage to 3.29V: enter image description here

And V3 at 5.75V increases the -ve voltage to 5.03V and causes Vout to flip from -4V to +4V (as desired. Vout is connected to the gate of a FET that pulls V3 to ground). The difference between the voltages is always approximately 0.8V: enter image description here

Calculating the voltage at the -ve terminal it should always be 4.7k/1M+4.7k *-5V = -23.4mV but this only seems to be true when V3 is close to zero.

Part of the original circuit: enter image description here

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  • \$\begingroup\$ PLS. Explain the purpose or "I/O specs" for your design. It appears to be some AGC \$\endgroup\$ Commented Apr 11, 2019 at 16:39

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The answer is in the fine print of the datasheet. (Note 2 on Page 5 bottom.)

Note 2: Differential input voltages greater than 1V will cause excessive current to flow through the input protection diodes unless limiting resistance is used.

This is referenced on Page 2 for ABSOLUTE MAXIMUM

Differential Input Current (Note 2) ..................... ±10mA

Therefore your solution is to limit input current using a series R on Vin-

  • such that the offset voltage from input bias current is negligible yet will not exceed Diff input current when you put such a high voltage (5V when comparing it to -xx mV)

\$V=I_{in}*Rs\$ where Iin differential must not exceed 10mA or even come close to this.(!)

Iin max = ±450 pA

The internal schematic has ESD protection diodes which you are overdriving with a "voltage source" with no current limit into a high impedance input.

enter image description here

Simple answer shown below.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ Ok I think I understand why. Adding a high value resistor in series with V3 and the +ve terminal drastically reduced the voltage increase (-ve terminal) when the differential inputs exceeded 1V but this also stopped Vout from flipping the voltage when V3 went above the supply rail. Any idea why this may prevent the op amp acting as a comparator? Thanks for the help. \$\endgroup\$
    – ChrisD91
    Commented Apr 11, 2019 at 16:25
  • \$\begingroup\$ Your reference voltage Vin- has to go negative to -23.4mV for the output to switch. not +5V or +1V The inputs must match at threshold of output comparator switching and never exceed input differential current for this device \$\endgroup\$ Commented Apr 11, 2019 at 16:31
  • \$\begingroup\$ Are you trying to design a DC ok signal? for Vee? \$\endgroup\$ Commented Apr 11, 2019 at 16:33
  • \$\begingroup\$ I'm currently just trying to understand how the circuit operates. It's quite big and an old design - the original designers are not around anymore. The output of U16b should pull Vout of U16a to ground if U16a latches high or low. It does this in the simulation if I don't have the suggested series resistor. *edited question with an additional schematic. \$\endgroup\$
    – ChrisD91
    Commented Apr 11, 2019 at 16:41
  • \$\begingroup\$ OK so I-in max= +/-10pA and R82=4k7 limits current until Diode D31 conducts. So what is the differential input voltage and current? neglible since D31 protects the input Vin- going to +5 \$\endgroup\$ Commented Apr 11, 2019 at 16:45

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