# Help with understanding op amp terminal voltages

I've got a circuit that I am simulating to help understand how a latch-up prevention circuit that is being used in a design works. The circuit:

My question: As i increase the DC voltage V3 at the -ve terminal the voltage at the +ve terminal also increases without any feedback loop. Could someone please explain this? Eg. V3 at 4V increases the +ve voltage to 3.29V:

And V3 at 5.75V increases the -ve voltage to 5.03V and causes Vout to flip from -4V to +4V (as desired. Vout is connected to the gate of a FET that pulls V3 to ground). The difference between the voltages is always approximately 0.8V:

Calculating the voltage at the -ve terminal it should always be 4.7k/1M+4.7k *-5V = -23.4mV but this only seems to be true when V3 is close to zero.

Part of the original circuit:

• PLS. Explain the purpose or "I/O specs" for your design. It appears to be some AGC Commented Apr 11, 2019 at 16:39

The answer is in the fine print of the datasheet. (Note 2 on Page 5 bottom.)

Note 2: Differential input voltages greater than 1V will cause excessive current to flow through the input protection diodes unless limiting resistance is used.

This is referenced on Page 2 for ABSOLUTE MAXIMUM

Differential Input Current (Note 2) ..................... ±10mA

Therefore your solution is to limit input current using a series R on Vin-

• such that the offset voltage from input bias current is negligible yet will not exceed Diff input current when you put such a high voltage (5V when comparing it to -xx mV)

$$\V=I_{in}*Rs\$$ where Iin differential must not exceed 10mA or even come close to this.(!)

Iin max = ±450 pA

The internal schematic has ESD protection diodes which you are overdriving with a "voltage source" with no current limit into a high impedance input.