I am studying the Programmable Logic Array (PLA) and Programmable Array Logic (PAL). I understood every detail I found about them including the implementation and difference between them. But I have a very simple question about their naming. Why did the early designer of such devices choose those close names for both of them? If the PLA appeared first then they designed a new device, why did they just swapped two words in the name from Programmable Logic Array (PLA) to Programmable Array Logic (PAL)? Do not you find it very confusing to differentiate between them? I did google search to find an answer to this question but I did not find any. Do you have any explanation?

  • \$\begingroup\$ It might just be a nuance you're missing if you're not a native English speaker. To me, they sound like distinctly different things even if I don't know exactly what the differences are. Not knowing exactly what the differences are between the two, PLA clearly sounds to me something like an FPGA or CPLD, whereas a PAL sounds like something different. \$\endgroup\$ – DKNguyen Apr 12 '19 at 18:43
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    \$\begingroup\$ See computerhistory.org/siliconengine/… for a short bit of the history. \$\endgroup\$ – jonk Apr 12 '19 at 18:45
  • \$\begingroup\$ Thank you @Toor, yes I am not a native speaker. Indeed I know that they are different two devices. But I am always confused which one is programmable and which is not. I cannot find any connection between the naming difference and the implementation difference. \$\endgroup\$ – Osama El-Ghonimy Apr 13 '19 at 18:06
  • \$\begingroup\$ Thank you @jonk, it is an interesting link. However, it does not answer my question about the naming. \$\endgroup\$ – Osama El-Ghonimy Apr 13 '19 at 18:06
  • \$\begingroup\$ That's why I didn't write it as an answer. I wasn't sure what exactly you wanted and if it was enough. \$\endgroup\$ – jonk Apr 13 '19 at 18:11

To summarize the link that jonk put in the comments: There are three ways to implement a generic programmable sum-of-products (AND gates followed by OR gates) function. In historical order, they are:

  • PROM Programmable Read-Only Memory - the word decoder (AND gates) are fixed, and the data (OR gates) are programmable.
  • PLA Programmable Logic Array - both the AND gates and the OR gates are programmable. This allows more complex functions than a straight PROM allows with a much more efficient implementation.
  • PAL Programmable Array Logic - the AND gates are programmable, but the OR gates are fixed. It was realized that the PLA was overkill for many simple functions that only needed a limited number of product terms per output, so fixing the OR structure allowed a much smaller chip.

The similarity of the last two names is mainly a historical artifact, and also probably a function of how the devices were marketed.

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  • \$\begingroup\$ Thank you @Dave for the summary. Till now, this is the most probable reason to be just naming for marketing. \$\endgroup\$ – Osama El-Ghonimy Apr 15 '19 at 16:37

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