Start by drawing the actual schematic of your full adder.
Second, your data is incomplete — you also need to know the clock-to-output delay of your FF.
Then you need to consider EVERY path through the circuit:
- from input to output
- input to clocked device (e.g., FF)
- clocked device to output
- clocked device to clocked device
And obviously, with clocked devices, you need to determine which of these paths put limits on the minimum clock period you can use. For example, even in a circuit that contains only FFs feeding each other, the minimum clock period is the sum of the clock-to-output and setup-to-clock delays. Any logic you insert into such a path simply increases the minimum clock period.
Just as an example, here's one way to build a full adder using AND, OR and NOT gates:
simulate this circuit – Schematic created using CircuitLab
As you can see, there are three different paths by which a signal travels from the A input to the Cout ouput:
- A → AND1 → OR3 → Cout (shortest)
- A → OR1 → AND2 → AND3 → OR3 → Cout
- A → AND1 → NOT1 → AND2 → AND3 → OR3 → Cout (longest)
You need to analyze each of these paths to determine what its total delay is. Then take the largest value and use that as the worst case A → Cout delay in your two proposed circuits. Note that the paths for the B input are the same, so you can reuse the same analysis there.
In contrast, there's only one path from Cin to Cout:
Add up these delays to get the Cin → Cout delay you can use in the larger circuits.
Then do the same kind of analysis for all of the paths from the inputs to the S output.
Note that when you look at a chip datasheet, they've done all of the internal adding-up for you and just tell you what the results are for every combination of input and output.