I want to compare performance of 4-bit full adder vs sequantial (serial ) adder with one D flip flop .. The two models are in the followig figures

Combinational adder:

Serial adder:

Lets say in gate level AND, OR and NOT gates will have time delay 30 ns, 20 ns and 10 ns, respectively. And the setup and hold time for D-flipflop are 10 ns and 5 ns, respectively. The problem is I am not sure how to compute the delay, or how to deal with the path that I should select. I have seen some videos in youtube and they were not helpful.

Can anyone please show me the way cause I want to make use of it .. Thanks in advance

  • 1
    \$\begingroup\$ Welcome to EE.SE! This appears to be a homework question. As such, you need to show us your work so far, and explain which part of the question you're having trouble with. For future reference: Homework questions on EE.SE enjoy/suffer a special treatment. We don't provide complete answers, we only provide hints or Socratic questions, and only when you have demonstrated sufficient effort of your own. Otherwise, we would be doing you a disservice, and getting swamped by homework questions at the same time. See also here. \$\endgroup\$ – Dave Tweed Apr 13 '19 at 13:36
  • \$\begingroup\$ Hi as please let me rewrite my requiest " have seen some videos in youtube and they were not helpful.Can anyone please show me the way cause I want to make use of it .. Thanks in advance" \$\endgroup\$ – Freeman Apr 13 '19 at 15:15

Start by drawing the actual schematic of your full adder.

Second, your data is incomplete — you also need to know the clock-to-output delay of your FF.

Then you need to consider EVERY path through the circuit:

  • from input to output
  • input to clocked device (e.g., FF)
  • clocked device to output
  • clocked device to clocked device

And obviously, with clocked devices, you need to determine which of these paths put limits on the minimum clock period you can use. For example, even in a circuit that contains only FFs feeding each other, the minimum clock period is the sum of the clock-to-output and setup-to-clock delays. Any logic you insert into such a path simply increases the minimum clock period.

Just as an example, here's one way to build a full adder using AND, OR and NOT gates:


simulate this circuit – Schematic created using CircuitLab

As you can see, there are three different paths by which a signal travels from the A input to the Cout ouput:

  • A → AND1 → OR3 → Cout (shortest)
  • A → OR1 → AND2 → AND3 → OR3 → Cout
  • A → AND1 → NOT1 → AND2 → AND3 → OR3 → Cout (longest)

You need to analyze each of these paths to determine what its total delay is. Then take the largest value and use that as the worst case A → Cout delay in your two proposed circuits. Note that the paths for the B input are the same, so you can reuse the same analysis there.

In contrast, there's only one path from Cin to Cout:

  • Cin → AND3 → OR3 → Cout

Add up these delays to get the Cin → Cout delay you can use in the larger circuits.

Then do the same kind of analysis for all of the paths from the inputs to the S output.

Note that when you look at a chip datasheet, they've done all of the internal adding-up for you and just tell you what the results are for every combination of input and output.

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