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After watching the excellent Carrie Anne's Crash Course Computer Science #6 (https://www.youtube.com/watch?v=fpnE6UAfbtU), I tried to design a Gated Latch in Logicly.

I played with it a little, and created a design that uses four gates, whereas Carrie Anne's uses six gates.

I tried it out in Logicly and it seems to work, although when the latch holds 1, and WRITE ENABLE is 0 - the output flickers.

So, can anyone please point out my mistake in the design? (and also explain if and how it relates to the flicker I see on Logicly).

Here is Carrie Ann's design, from the Youtube video mentioned above:

Carrie Ann's Gated Latch

Here is mine:

My Gated Latch

Thank you!

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  • \$\begingroup\$ Your circuit oscillates. Start with both inputs 0, then toggle the data to a 1. Now toggle the enable to a 1. Let this settle and everything is fine, so far. The output is a 1. But the problem occurs when you now turn the enable off, to a 0. At this point your AND and OR at the output end of things may very well oscillate. (If you are curious about why, just "single step" so to speak one gate delay at a time.) \$\endgroup\$ – jonk Apr 14 at 0:56
  • \$\begingroup\$ Thanks, @jonk :) If you post this as an answer, I will mark it as accepted... \$\endgroup\$ – obe Apr 14 at 1:06
  • \$\begingroup\$ It's good that you understand. It takes time to prepare an answer well and set up the exact details so that others looking on might also feel as though they too understand. The work involved is probably worth the trouble, since it may help more than one person in the world. So I may bother. But it may be an hour before I do that. \$\endgroup\$ – jonk Apr 14 at 1:10
  • \$\begingroup\$ Oscillations occur in logic with a negative feedback loop but not a positive feedback loop, then it is a latch. There are no negative feedback loops. But in Analog it oscillates with positive feedback loops if it is AC coupled \$\endgroup\$ – Sunnyskyguy EE75 Apr 14 at 1:57
  • \$\begingroup\$ Use a large R eg 100K to gnd on each switch and other side to V+. So On is HI \$\endgroup\$ – Sunnyskyguy EE75 Apr 14 at 2:06
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As I mentioned in the comments above, your circuit can oscillate.


Setting DATA IN = 1

Let's start with both inputs 0, then toggle the data to a 1. Those two steps are shown below, in succession, with the signals fully propagated to the output. There's no problem, yet:

enter image description here


Toggling ENABLE to 1, then 0

Set the enable to 1 and let the logic settle once again. Everything is still fine and the output is now a 1.

But then let's begin the process of oscillation by setting enable back to 0 (to complete the data latching event.)

Starting with step 4, I'm slowing down the propagation so that the signals change at the inputs of the first two gates, only. Then we will evaluate just those two gates for the following step (not show yet, but in step 5) in order to work out their outputs (which will be inputs to the next two gates):

enter image description here

The output is a 1. But the problem occurs when you now turn the enable off, to a 0. At this point your AND and OR at the output end of things may very well oscillate. (If you are curious about why, just "single step" so to speak one gate delay at a time.)


Propagation through the gates

In step 5 below, the inputs to the first two gates are accepted and then processed by those first two gates on the left, changing their outputs.

In step 6 below, the inputs to the final two gates are accepted and then processed by those final two gates on the right, changing their outputs. Please note that this also changes their inputs, again:

enter image description here


Oscillation

In step 7 below, note that in one more incremental step (one gate delay) we are back to the same situation as we were in step 5 above:

enter image description here

This is why there may be oscillation. If you've returned to the same state as step 5, which will be followed by step 6 and then returned back to step 5 again, then this implies oscillation as a possible result.

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  • \$\begingroup\$ many logic circuits will misbehave if given pulses on the input that are too short (runt pulses), \$\endgroup\$ – Jasen Apr 14 at 3:22
  • \$\begingroup\$ @Jasen This is a hand-stepped example and obviously I've treated each gate as having exactly the same propagation delays. But hopefully it helps explain to the OP what was being seen. \$\endgroup\$ – jonk Apr 14 at 3:30
  • \$\begingroup\$ I see now the bottom and can't get set until the load pulse is turned off. \$\endgroup\$ – Jasen Apr 14 at 3:50
  • \$\begingroup\$ In CD4xxx CMOS, this will not oscillate, as the AND, OR gate rise is always less than Prop delay due to extra buffers to NANDs and race condition is guaranteed not to oscillate and will always latch unless in the input pulse is too small due to the rise time to either input. \$\endgroup\$ – Sunnyskyguy EE75 Apr 14 at 10:26
  • \$\begingroup\$ @SunnyskyguyEE75 I wanted to explain why the OP was getting the simulation results they received. That was the only target I had in mind. \$\endgroup\$ – jonk Apr 14 at 15:06
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Any timing diagram or metastable or race conditions for a latch must define the logic family and the dependencies on Vcc, Prop Delay, tp, Transition time, tt ( slew) load capacitance, Vcc tolerance, temperature.

I doubt CMOS uses either of these configurations for a gated latch but it is often taught and ignoring the above. If we assume zero time, we can expect false timing results as every path has a delay. Flip Flops have used transmission gates for logical functions with better performance in CMOS FF's and not what is often shown in textbooks. Since FETs invert all the gates are inverting so a non-inverting logic needs to be NAND NOR with INV on outputs. The parts with B suffix use at least 2 INV on output to prevent feedback from output loads getting inside the edge sensitive inputs and providing more gain-bandwidth.

Your Design

  • with suitable RC filters to emulate 5V CMOS rise time and prop delay.
  • using 1MHz square wave clock and a higher frequency (1.54MHz) to test with various setup and hold times.

enter image description here

Below using NAND with inverter and defined slew rate to look more like original CD4xxx family and see the changes. It still doesn't latch as you might want.

enter image description here

BELOW is your top reference Video Circuit in the Video, ... which also does not latch properly using NAND, NOR+INV
...instead of AND OR which do not exist in CMOS without inverters.

enter image description here

Here is a variation which works as a gated memory cell on the rising edge of Clock as opposed to a latch with the trailing edge of Enable. It also has R-S inputs. This is logically the same as the D FF..

Here I speed up the clock and Data x10 to 10 MHz, 15 MHz

enter image description here

Final Thoughts.

I realize this too much to throw at a rookie. But when CMOS first came out, I worked in my final year of undergraduate EE studies, part-time for Earth Sciences building some Ph.D. Physics students design of a presettable timer recorder for Seismic signals all in CMOS, it didn't work due to OEM timing variations with Race conditions. But I fixed them. In my 2nd job, I had to do a Design Review of complex motherboards with manual timing analysis worst-case for race conditions that were far more complicated than below. But if you break it down to simple chunks of timing diagrams like the datasheets on paper, then it's doable, but not so easy with a mouse and keyboard.

So just remember to define all assumptions in your design before doing it. i.e. Specs, just like the ones in the datasheets. These are the Rules of Logic give the greatest chance of success.

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  • \$\begingroup\$ Here's a link for one of my Falstad simulations above tinyurl.com/y42qgv7r The gates are ideal with no prop delay, the Inverters have slew rate control ( right Mouse). The Trace display can be dragged up and then Edit > Centre Circuit. \$\endgroup\$ – Sunnyskyguy EE75 Apr 14 at 16:46
  • \$\begingroup\$ TOO bad noone appreciates the power of simulation and pictures to prove why it is not a latch. If you cannot read a timing diagram in a datasheet, then you are not ready to design one. The real problem is there is no Spec. truth table or logic rule, or functional description of this cct. . \$\endgroup\$ – Sunnyskyguy EE75 Apr 15 at 4:03
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The problem is that your circuit can't load a 1 into both of the latch gates,

When you turn the write and data inputs on the and gate gets a 0 on one input so it stays off until the write enable goes away.

Oring in the data and gatw with the not resiult allows the adn gat to be set during the write cycle resulting both latch gates being set or cleared as appropriate.

schematic

simulate this circuit – Schematic created using CircuitLab

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