# Bootstrap cap value and how it relates to fsw and duty cycle?

I am designing a synchronous buck converter with mppt. I have a question about the bootstrap capacitor value. Knowing that the duty cycle and fsw are dependent on this value. What is the best approach to this?

note that Vs of the high side switch is changing as the duty cycle change, thus the input voltage changes since its the solar panel voltage.

• Related: Bootstrap Capacitor Selection, Calculation for the Boot Strap capacitor. Application notes: Fairchild AN-6076, Bootstrap Circuit Design Manual. – Nick Alexeev Apr 15 at 2:21
• What is your low voltage supply for the bootstrap (typically +15 or something like that)? – Spehro Pefhany Apr 15 at 3:18
• @SpehroPefhany , it is 15V – abu khlad Apr 15 at 3:27
• The bootstrap cap doesn't really care about the input voltage, it cares about switching frequency and gate charge and duty cycle and the difference between the 15V supply and Vos2. When the cap is being charged that's the voltage. When it's being used, it is referenced to the source of Q1. – Spehro Pefhany Apr 15 at 3:29
• @SpehroPefhany now in my case, I assume the gate charge and switching frequency are constant, but for mppt, the duty cycle will change, what consideration do you think i have to take for that. – abu khlad Apr 15 at 3:32

## 1 Answer

The C_boost impedance must be lower than the load capacitance but not too much higher.

The first step is the capacitor C value must be bigger than the load, then it is charges up the V+ rail voltage on negative swings when the low side Nch FET conducts. The next step is an internal positive rectifier to make a charged voltage to drive the gate well above the V+ rail.( such that Vboost=Vgs=2~3*Vgs(th) to achieve low RdsOn). The low side PWM does the work of pumping the charge to the Boost cap for the high side Nch can start working.

But you know Q=CV so the formulae shows all the load charges that must be transferred by using a boost capacitance 2x or twice the maximum load.

Zc=(2pif*C)^-1 to capture most of the PWM swing, yet if it is too big that it overloads the negative Nch FET, unless there is some soft start.

This just gives some intuition to the formulae in the design manuals in comments.

Here is a simple capacitive divider to a step pulse to show a linear representation, even though the FET gate capacitance rises sharply at threshold voltage of conduction

simulate this circuit – Schematic created using CircuitLab

• thank you for your reply. Is this case true when the voltage is present like a battery? – abu khlad Apr 15 at 8:46
• Yes Cboot=Qtotal / ΔVboot and Qtotal=Qgate + I(leakage) * t_on + Q_ic – Tony Stewart Sunnyskyguy EE75 Apr 15 at 14:53
• thank you very much for your answer. I really cannot figure out delta_Vboot and Q_ic. I assume I (leakage) is zero for ceramic. like for example, if Vin range is 37 to 18V and v_battery is 6 to 8V. I also see a lot of people paralleling Cboot capacitor with a electrolytic capacitor of some value? – abu khlad Apr 16 at 1:09
• ΔVboot is less than Vdd by the diode switch voltage drop Qic is often given for the internal charge pump, if you follow best design examples in commercial solutions, that ought to be fine. – Tony Stewart Sunnyskyguy EE75 Apr 16 at 1:11
• I really appreciate your very clear explanation. Thank you very much! – abu khlad Apr 16 at 2:55