The C_boost impedance must be lower than the load capacitance but not too much higher.
The first step is the capacitor C value must be bigger than the load, then it is charges up the V+ rail voltage on negative swings when the low side Nch FET conducts. The next step is an internal positive rectifier to make a charged voltage to drive the gate well above the V+ rail.( such that Vboost=Vgs=2~3*Vgs(th) to achieve low RdsOn). The low side PWM does the work of pumping the charge to the Boost cap for the high side Nch can start working.
But you know Q=CV so the formulae shows all the load charges that must be transferred by using a boost capacitance 2x or twice the maximum load.
Zc=(2pif*C)^-1 to capture most of the PWM swing, yet if it is too big that it overloads the negative Nch FET, unless there is some soft start.
This just gives some intuition to the formulae in the design manuals in comments.
Here is a simple capacitive divider to a step pulse to show a linear representation, even though the FET gate capacitance rises sharply at threshold voltage of conduction
simulate this circuit – Schematic created using CircuitLab