# Identify the problems in this Verilog snippet

I think that the code below is wrong because it uses blocking (=) instead of non-blocking (<=) assignments but since there is only one statement in the always block is this an issue?

Also, it is sensitive to op but it also updates op within the always block, will this create some sort of loop condition?

Are there other problems with it?

always @ (a or op)
begin
op = a + b;
end


op should not be in the sensitivity list but it does not hurt.