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I'm getting the above error message, and I don't understand what I'm doing wrong.

I've only found one reference to that message, and it led me down this rabbit hole of trying to apply the safe_implementation attribute to the type, record, and/or signals. Nothing I tried seemed to help. If this is the solution, could you please include what to apply it to?

My testing showed that changing if lookup_b.address=t_opt*e* then to if lookup_b.address=t_opt*a* then fixes the problem... if that's what I want to do. I feel this is a big hint, but am not quite able to interpret it...

Here is my VHDL (stripped down as much as possible, but so it will still produce this error) and the resulting error log:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

USE IEEE.NUMERIC_STD.ALL;

entity testit is Port ( 
    CLOCK_32MHZ : in  STD_LOGIC;
    SWITCH: in std_logic;
    LED: out std_logic);
end testit;

architecture Behavioral of testit is

    SUBTYPE index_type  IS INTEGER RANGE 0 to 2;
    TYPE unused_type                IS (t_uopta, t_uoptb);

    TYPE lookup_a_record    is record
        lookup_b_index:     index_type;
        unused:             unused_type;
    END RECORD lookup_a_record;

    TYPE lookup_a_array IS ARRAY(0 to 2) OF lookup_a_record;

    CONSTANT lookup_a_table: lookup_a_array := (
        (  0, t_uopta),
        (   2, t_uoptb ),
        (   2, t_uoptb )
    );

    TYPE choice_type            IS (t_opta,t_optb, t_optc, t_optd, t_opte);

    TYPE lookup_b_record is record
        address:             choice_type;
        unused:              unused_type;
    END RECORD lookup_b_record;

    TYPE lookup_b_array IS ARRAY(0 to 2) OF lookup_b_record;

    CONSTANT lookup_b_table: lookup_b_array := (
        (t_opta        , t_uopta), 
        (t_opte         , t_uoptb),
        (t_opte         , t_uoptb)
    );

    signal lookup_a: lookup_a_record := (  0, t_uopta)      ;
    signal lookup_b: lookup_b_record := (t_opte         , t_uoptb);

    signal key_a: integer range 0 to 1;

begin
    key_a <= 0 when SWITCH='0' else 1;

    lookup_a <= lookup_a_table(key_a);

    lookup_b <= lookup_b_table(lookup_a.lookup_b_index);

    update_output: process(CLOCK_32MHZ) begin
        if rising_edge(CLOCK_32MHZ) then
            if lookup_b.address=t_opte then
                LED<='1';
            else
                LED<='0';
            end if;
        end if;
    end process;

end Behavioral;

Compilation log shows:

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "/home/jbloem/bbc_5/testit.xst" -ofn "/home/jbloem/bbc_5/testit.syr"
Reading design: testit.prj

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/jbloem/bbc_5/testit.vhd" in Library work.
Entity <testit> compiled.
Entity <testit> (Architecture <Behavioral>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <testit> in library <work> (architecture <Behavioral>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <testit> in library <work> (Architecture <Behavioral>).
Entity <testit> analyzed. Unit <testit> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <testit>.
    Related source file is "/home/jbloem/bbc_5/testit.vhd".
WARNING:Xst:646 - Signal <lookup_b.unused<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <lookup_a.unused<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <lookup_a.lookup_b_index> of Case statement line 0 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safe
ly, you can:
    - add an 'INIT' attribute on signal <lookup_a.lookup_b_index> (optimization is then done without any risk)
    - use the attribute 'signal_encoding user' to avoid onehot optimization
    - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Using one-hot encoding for signal <lookup_a.lookup_b_index>.
    Using one-hot encoding for signal <lookup_b.address>.
INTERNAL_ERROR:Xst:hdltool.c:4862:1.209 -  Signal lookup_b.address, 0 ones:XX 
INTERNAL_ERROR:Xst:hdltool.c:4863:1.209 -  To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com 
--> 


Total memory usage is 506408 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    1 (   0 filtered)


Process "Synthesize - XST" failed
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  • \$\begingroup\$ Your code synthesised without error on Vivado 2018.3. This may be an issue with your version of Xilinx tools. \$\endgroup\$ – amb Apr 30 at 9:29
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I could be totally off-base, but I have a hunch that this must have something to do with undefined values for the state arising from out-of-range indices into your tables. I would try adding a condition to prevent out-of-range values, and provide a default table value in these cases, something like:

if(lookup_a.lookup_b_index <= 2) then
   lookup_a <= lookup_a_table(key_a);
else
   lookup_a <= 0
end if;

I think because lookup_type is range 0 to 2, it will instantiate a 3-bit value which of course includes possible values outside your table range.

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  • \$\begingroup\$ I don't have access to my other computer right now, but I will try this. \$\endgroup\$ – AMADANON Inc. Apr 28 at 20:22

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