0
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I made the below counter and stimulus/testbench and it works fine.

module half_adder(
    input in1,
    input in2,
    output sum,
    output carry
    );
 xor(sum,in1,in2);   
 and(carry,in1,in2);   
endmodule

module counter(
   input  [3:0] a,
    input  clk,
    input add,
    output [3:0] r
);
wire c0,c1,c2,c3;

half_adder h1(a[0],add,r[0],c0);
half_adder h2(a[1],c0,r[1],c1);
half_adder h3(a[2],c1,r[2],c2);
half_adder h4(a[3],c2,r[3],c3);

endmodule

module stimulus;
reg [3:0]value_i;
wire [3:0]value_o;
reg clk,reset,count_i,preset,timeout_o,add;

counter co1(value_i,clk,add,value_o);
initial
begin
value_i = 4'h0; 
clk = 1;
reset=0;
add = 1;
end


always
#20 clk = !clk;
endmodule

Now I would like to increment continuously until 4'hF and stop. The logic is to perform a reduction AND on the value_o and update the add to be 1.

I have tried using a while loop like

while((&value_o)==0)
add = 1;

But Xilinx Vivado Simulation just gave value_o to be 1 always.

My next idea is to use a generate loop. Like

generate 
if((&value_o)==0)
 counter co2(value_o,clk,1,value_o2);

But I do not know how to update value_i of co2 to be value_o of co1.And where should the generate loop be placed? I assume it should be in it's own? (if it makes sense). What other ways can I do this?

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  • \$\begingroup\$ What's wrong with a 4-input AND gate? \$\endgroup\$ – Elliot Alderson Apr 15 at 15:52
  • \$\begingroup\$ @ElliotAlderson Isn't it a simpler way to do the reduction AND on value_o? \$\endgroup\$ – Yasha Apr 15 at 15:56
  • 2
    \$\begingroup\$ My point is that an AND reduction of four bits is just a 4-input AND gate. If you are writing structural code, why not use a structural element? \$\endgroup\$ – Elliot Alderson Apr 15 at 16:04
  • \$\begingroup\$ That makes a lot of sense. I'm new to verilog and it's easy to get carried away from the modelling type being used. \$\endgroup\$ – Yasha Apr 15 at 16:07
1
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An AND reduction of 4 bits can be performed using a 4-input AND gate, and is consistent with your intention of writing structural code.

Having said that, the block that you call counter isn't a counter at all...it is just a 4-bit adder. To make it behave as a counter you need to add a 4-bit register that will load the output of the adder on every clock edge. The input to the adder then comes from the output of the register.

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  • \$\begingroup\$ That is the basic idea and what I've written. But I get the register implementation. I have implemented it and it's a progress. \$\endgroup\$ – Yasha Apr 15 at 16:33

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