How to create continuously incrementing counter in structural modelling?

I made the below counter and stimulus/testbench and it works fine.

module half_adder(
input in1,
input in2,
output sum,
output carry
);
xor(sum,in1,in2);
and(carry,in1,in2);
endmodule

module counter(
input  [3:0] a,
input  clk,
output [3:0] r
);
wire c0,c1,c2,c3;

endmodule

module stimulus;
reg [3:0]value_i;
wire [3:0]value_o;

initial
begin
value_i = 4'h0;
clk = 1;
reset=0;
end

always
#20 clk = !clk;
endmodule


Now I would like to increment continuously until 4'hF and stop. The logic is to perform a reduction AND on the value_o and update the add to be 1.

I have tried using a while loop like

while((&value_o)==0)


But Xilinx Vivado Simulation just gave value_o to be 1 always.

My next idea is to use a generate loop. Like

generate
if((&value_o)==0)
counter co2(value_o,clk,1,value_o2);



But I do not know how to update value_i of co2 to be value_o of co1.And where should the generate loop be placed? I assume it should be in it's own? (if it makes sense). What other ways can I do this?

• What's wrong with a 4-input AND gate? – Elliot Alderson Apr 15 '19 at 15:52
• @ElliotAlderson Isn't it a simpler way to do the reduction AND on value_o? – Yasha Apr 15 '19 at 15:56
• My point is that an AND reduction of four bits is just a 4-input AND gate. If you are writing structural code, why not use a structural element? – Elliot Alderson Apr 15 '19 at 16:04
• That makes a lot of sense. I'm new to verilog and it's easy to get carried away from the modelling type being used. – Yasha Apr 15 '19 at 16:07

Having said that, the block that you call counter isn't a counter at all...it is just a 4-bit adder. To make it behave as a counter you need to add a 4-bit register that will load the output of the adder on every clock edge. The input to the adder then comes from the output of the register.