# Address decoding different bank sizes in 64K memory

I'm doing a small Motorola 6809-based computer project, and since I'm a bit rusty when it comes to boolean algebra I'm wondering if I'm doing my address decoding a bit too complicated for my simple use case.

What I want to achieve is the memory mapping show below. I've divided it in this way since I have four ICs (2 x 62256 32K RAM, MC68B50 UART, 8K 28C64 ROM) mapped into memory.

0000-7FFF : 32K RAM (LO-RAM)
8000-BFFF : 16K RAM (HI-RAM)
C000-DFFF : UART (minimally decoded)
E000-FFFF : 8K ROM (monitor)


I'm thinking of using a 2-4 decoder to divide the upper 32K of memory where the first 16K reserved for the HI-RAM. For simplicity's sake I'm lazily mapping the UART into an entire 8K block, and using the last 8K block for the ROM.

I've drawn up the decoding logic as below which requires three 74-series logic which gets the job done but somehow feels like it could be reduced:

This if I'm thinking correctly would produce the following truth table which I believe corresponds to my memory map:

Am I making this more complicated than it needs to be? Could I reduce the memory decoding logic?

• You could use a straight AND gate for U7 (XNOR works though in this case). There are single (and universal) gate devices available for those if you are not using the other gates elsewhere. As to the logic, it is about as minimal as it can get. Apr 16, 2019 at 12:08
• That's true, it would only differ on the case were both inputs are low (which they will never be using the decoder). Apr 16, 2019 at 12:12
• You only need two chips. Either use another XNOR as an inverter and save having to use a 74HCT04, or use the other half of the 74HCT139 to replace the XNOR. Apr 16, 2019 at 12:20
• @Finbarr Oh I didn't even think of using the /HIRAM outputs as inputs to the other part of the decoder, this makes it a lot simpler. Apr 16, 2019 at 12:26
• The neatest way is actually to program a PLD like the ATF16V8 to do the lot. It all depends on your design goals. Apr 16, 2019 at 12:33