I'm trying to design an interfacing board that is used between a micro-controller and a phone simulator (a picture of the schematics is attached). The 44VDC is used for the phone simulator to detect phone off-hook state; this state is triggered as the GPIO pin sends a signal and turn on the M1 NMOS.

And the AC signal V3 is used to model the ringing AC current generated from the phone simulator and send to micro-controller side circuit. This AC signal is converted to DC and triggers optocoupler which should pull the signal at gpio pin from High to Low. However, it doesn't work as expected.

I'm completely puzzled by the voltage levels measured at those specific nodes near the Rectifier circuit. Also, I don't understand why the C2 capacitor doesn't completely block the 44VDC. I needed to block this DC because I don't want the capacitor C1 to be pre-charged.

Also, I have to pick a extremely High resistance for the pull-up resistor R1 to drop the V_drain to Logic low level. If I use 10k resistor the V_drain will stay at Logic level high when the BJT inside the optocupler is triggered. Need some help. Thank you so much, everyone.

enter image description here

  • 1
    \$\begingroup\$ Your AC source (V3) has zero DC resistance. The electrons aren't leaking through C2, they're going through your diode bridge. \$\endgroup\$
    – TimWescott
    Apr 16, 2019 at 19:56
  • \$\begingroup\$ In your text you mention "V_drain", but I don't see any node with that name in your circuit. \$\endgroup\$
    – The Photon
    Apr 16, 2019 at 19:58
  • \$\begingroup\$ Thank you all for your help. yeah, the dc issue has gone. but the pull up resistor still doesn't produce the logic low level voltage. Any ideas why? thank you. you guys are the best \$\endgroup\$
    – Jung_Zheng
    Apr 16, 2019 at 20:16
  • \$\begingroup\$ What is the current through R7 when V3 is running? That, multiplied by the Current Transfer Ratio (CTR) of the 4N25 will get you how much current you should expect the output transistor to sink. Check to make sure you have a decent amount of current (>1mA at least). Also, R5 looks really weird, normally that pin of the optocoupler would be floating. You may be short-circuiting the base of the output transistor. \$\endgroup\$
    – W5VO
    Apr 16, 2019 at 20:54
  • \$\begingroup\$ @W5VO, thanks. You are absolutely right. it was the current that's extremely low, about less than 1pA. And per your feedback, I switched the 6-pin optocoupler to a 4-pin opto-coupler so that I don't need to worry about the connection for base terminal. But can I ask why in this case, do we want the base to float when the internal BJT is not triggered? I don't know much about micro electronics, but I always hear people say that don't make a terminal float. So thank you for explaining. also, what would you recommend to increase the current without affecting the AC to DC rectification. thank you \$\endgroup\$
    – Jung_Zheng
    Apr 18, 2019 at 18:19

1 Answer 1


I'm completely puzzled by the voltage levels measured at those specific nodes near the Rectifier circuit. Also, I don't understand why the C2 capacitor doesn't completely block the 44VDC.

V3 is a 0V source in DC simulation, so it provides a path for currents or voltages from one side of C2 to get through to the other.

You could put another capacitor in series with V3 to avoid this.

  • \$\begingroup\$ thank you so much. It solve the DC problem. But the voltage across the pull up resistor still doesn't drop downto logic low level. any ideas? thanks \$\endgroup\$
    – Jung_Zheng
    Apr 16, 2019 at 20:14
  • \$\begingroup\$ @Jung_Zheng, I don't understand that part of your question. It might help to (1) break up your question into paragraphs to make it easier to read. (2) Explain which node you mean by "V_drain". \$\endgroup\$
    – The Photon
    Apr 16, 2019 at 20:19
  • \$\begingroup\$ Hi @The_Photon, sorry about that. I'm new to StackExchange. Still trying to learn how to post questions effectively. is there any way that I can post images without posting up another New question ? thank you. And by V_Drain, I meant the voltage at GPIO_ringing, as this port is connected to the Drain terminal of the BJT inside the optocoupler. Thanks again for your help \$\endgroup\$
    – Jung_Zheng
    Apr 16, 2019 at 20:24
  • \$\begingroup\$ @Jung_Zheng, click "edit" beneath the question text and you can add that information to your question. \$\endgroup\$
    – The Photon
    Apr 16, 2019 at 21:17
  • \$\begingroup\$ @The_Photon, in your previous response you said "the AC-source V3 is a 0V source in DC 'simulation'", then does that mean if I actually implemented the circuit with breadboard, the problem will not occur? Thank you so much. \$\endgroup\$
    – Jung_Zheng
    Apr 18, 2019 at 18:23

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.