I want a free tool for finding the observability of signals in a VHDL or verilog code. Which tool do you know for this?


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  • \$\begingroup\$ What do you mean "observability of signals"? It's clear in the code where you can see the signals. If you mean to simulate the signals, that depends on which FPGA you are designing for, Lattice, Xilinix and Altera all have their own which are sometimes free, depending on what you're doing with it. \$\endgroup\$ – Puffafish Apr 17 at 14:18
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    \$\begingroup\$ @Puffafish: Observability has a very specific meaning in the context of fault analysis and test coverage. Go look it up. \$\endgroup\$ – Dave Tweed Apr 17 at 14:56
  • \$\begingroup\$ @Puffafish Even ignoring the correct definition of observability, the statement "It's clear in the code where you can see the signals" doesn't hold any water in the year 2019. \$\endgroup\$ – DonFusili Apr 18 at 10:14
  • \$\begingroup\$ Thanks, but I have some big codes and I want to automatically find the observability precentage of signals in my Verilog code. \$\endgroup\$ – user3637733 Apr 18 at 10:16

Yes, such tools exist.

Ironically, IEEE has a paper, "Free and open source fault tree analysis tools survey", which you have to pay to see.

A quick search turns up things like SCRAM and OpenFTA.

  • \$\begingroup\$ From the abstract of the linked article, they discuss OpenFTA, OpenAltaRica, and ALD Fault Tree Analyzer. IEEE Xplore is not working for me right now. \$\endgroup\$ – W5VO Apr 17 at 16:14
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    \$\begingroup\$ Research gate: researchgate.net/publication/… \$\endgroup\$ – laptop2d Apr 17 at 17:01
  • \$\begingroup\$ Thanks, I have just downloaded SCRAM. But it seems that it does not get vhdl or verilog code. Am I right? I wrote some verilog codes and I want to find the observability and controllability of my code \$\endgroup\$ – user3637733 Apr 18 at 10:05
  • \$\begingroup\$ I doubt that "observability and controllability" of the abstract functionality described in HDL is a well-defined concept. It seems to me that you would have to synthesize the code for a particular target technology, and then you can talk about observability and controllability of the resulting implementation. \$\endgroup\$ – Dave Tweed Apr 18 at 11:16

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