I want a free tool for finding the observability of signals in a VHDL or verilog code. Which tool do you know for this?
closed as off-topic by Elliot Alderson, Leon Heller, RoyC, Greg, Finbarr Apr 20 at 7:54
This question appears to be off-topic. The users who voted to close gave this specific reason:
- "Questions seeking recommendations for specific products or places to purchase them are off-topic as they are rarely useful to others and quickly obsolete. Instead, describe your situation and the specific problem you're trying to solve." – Elliot Alderson, Leon Heller, RoyC, Greg, Finbarr
Yes, such tools exist.
Ironically, IEEE has a paper, "Free and open source fault tree analysis tools survey", which you have to pay to see.