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I am attempting to create an output that goes on for a certain amount of time an then goes low for a certain amount of time and my out simply won't simulate.

Attached is my code, test bench, and simulation.

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  • \$\begingroup\$ You never assert rst so the state machine never goes to a known state from which it can switch into other states like you want. \$\endgroup\$ – The Photon Apr 18 at 2:09
  • \$\begingroup\$ how does one assert in verilog ? \$\endgroup\$ – helpneeded Apr 18 at 2:22
  • \$\begingroup\$ In your testbench, don't just set rst to 0. Set it to 1 initially, then after some time change it to 0. (if this doesn't work, then you might need to actually change it 0-1-0 to be sure of generating a posedge on rst) \$\endgroup\$ – The Photon Apr 18 at 2:25
  • \$\begingroup\$ Hmm I did this and nothing changed :( \$\endgroup\$ – helpneeded Apr 18 at 2:31
  • \$\begingroup\$ Did you try setting rst to 0, then 1, then 0? \$\endgroup\$ – The Photon Apr 18 at 2:39
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My first time doing verilog here is the code

The mistakes were as follows:

  1. Your count, wasn't initiated, so it was adding uknown with a +1 which returned an unknown; i also took the liberty initiated state as well.
  2. It did not know what to do when the state was 3'b000, you had the following covered 1,2,4; (you could use the "default" in case statement in verilog and set it to a known state? )

Suggestions :

  • I separated out the reset from the case logic, makes more sense to me that way

  • Might want to add a reset toggle to your test bench, within the first 10 ns or so as was suggested

the code is as follows

`timescale 1ns / 1ps


module clocksignal(
    input clk,
    input rst,
    output out
    );

    reg [5:0] count =5'b00000;
    reg [2:0] state =3'b000;
    reg w_output;

    always @(posedge clk, posedge rst) begin
        if (rst == 1) begin
            state <= 3'b000;
            count <= 5'b00000;
            end
        else
            case(state)
                3'b000 : 
                    state <= 3'b001;
                3'b001 : 
                    state <= 3'b010;
                3'b010 : 
                    if (count < 29) 
                        count  <= count + 1;
                    else if (count ==29 ) begin
                        state <=3'b100;
                        w_output <= 1;
                        count <= 0;  
                    end                     
                3'b100 : 
                    if (count < 42) begin
                        count <= count + 1;
                        w_output = 1;
                    end 
                    else if (count == 42) begin
                        count <= 0;
                        w_output <= 0;
                        state <= 3'b001;
                    end
             endcase
    end

    assign out = w_output;
endmodule

Simulation

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  • \$\begingroup\$ You should also include out and w_output in the reset statement to avoid the red lines. w_output should also be assigned an initialization value before reset just as you did with count and state. Posting the test bench you used might also be helpful to the OP unless you used the same one that OP posted \$\endgroup\$ – Simeon R Apr 18 at 10:46

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