I am attempting to create an output that goes on for a certain amount of time an then goes low for a certain amount of time and my out simply won't simulate.
Attached is my code, test bench, and simulation.
My first time doing verilog here is the code
The mistakes were as follows:
I separated out the reset from the case logic, makes more sense to me that way
Might want to add a reset toggle to your test bench, within the first 10 ns or so as was suggested
the code is as follows
`timescale 1ns / 1ps module clocksignal( input clk, input rst, output out ); reg [5:0] count =5'b00000; reg [2:0] state =3'b000; reg w_output; always @(posedge clk, posedge rst) begin if (rst == 1) begin state <= 3'b000; count <= 5'b00000; end else case(state) 3'b000 : state <= 3'b001; 3'b001 : state <= 3'b010; 3'b010 : if (count < 29) count <= count + 1; else if (count ==29 ) begin state <=3'b100; w_output <= 1; count <= 0; end 3'b100 : if (count < 42) begin count <= count + 1; w_output = 1; end else if (count == 42) begin count <= 0; w_output <= 0; state <= 3'b001; end endcase end assign out = w_output; endmodule