# common source pole calculation vs. simulation

I would like to compare my pole simulation results to my hand calculations, I'm receiving quite a big error. when simulating a Common Source stage without output capacitance load there is a big difference between the simulated and the calculated poles, when I'm adding a capacitor load the output pole is similar but the input (which didn't change) is not... maybe I didn't model the MOSFET correctly? ]3

When you add the 10 pF capacitor $$\C_{out}\$$ at the output it will dominate the overall transfer function. This is to be expected as that 10 pf is around 1000 times larger in value compared to any other capacitance present in the NMOS. Even the "amplification" (Miller effect) of $$\C_{gd} * gm * R_d\$$ will not result in anything close to 10 pF.
Without that $$\C_{out}\$$ there are many capacitors which come into play. Note how many capacitor values the model lists. Note that there's a $$\C_{gd}\$$ but also a $$\C_{dg}\$$! These capacitors are in parallel in the model. It isn't trivial to determine the values of $$\C_{gs}\$$ and $$\C_{gd}\$$ from the model which you would need in a simple small signal equivalent circuit.
Another complication you bump into is that the poles you simulate when you do not have a $$\C_{out}\$$ capacitor, are close to the $$\f_t\$$ of the transistor. In the simulator model $$\f_t\$$ is determined by many different capacitors, in a simple small signal model for hand calculations $$\f_t\$$ is determined by only a few capacitors. So linking the model to hand calculations requires a careful combination of the capacitors in the model. That isn't easy with today's complex models.