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After power up in an ASIC, is it save to assume that all flipflops are in a stable state ('0' or '1')? I do not care in which stable state they are, but it is crucial that all metastability has resolved. Adding resets would come at a high cost as these flipflops are part of a clock divider, where all the resets would need to be synchronised to intermediate clocks I do not use. Furthermore, all flipflops are T-flipflops. The time scale in which the flipflops have to resolve their state is in the order of milliseconds as all the power up circuitry like crystal has to start before.

I did read Output of a D flipflop upon power up?, but for me it is more the question about the timescale after which I can assume the flipflops to have resolved or how I could calculate it.

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  • \$\begingroup\$ Boring answer is that it depends on PVT and the cells you are using. Simulation is the only approach to this, unfortunately. \$\endgroup\$ – awjlogan Apr 18 at 9:27
  • \$\begingroup\$ I have never seen anybody worry about metastability on startup. A system reset should be orders of magnitude longer than any metastability, so the system should ignore signals that haven't settled yet. Also, if your divider clock is running, that should quickly resolve any metastability. Note that metastability is a rare but real issue, but this isn't a scenario where you will encounter it. \$\endgroup\$ – Mattman944 Apr 18 at 9:43
  • \$\begingroup\$ I don't think anyone can guarantee that all of your flip-flops will have resolved in any specific period of time. As with any metastability, all you can do is provide a statistical estimate of the likelihood that a flip-flop has resolved in a given length of time. That's why simulators initialize flip-flops to X. By the way, "PVT" means Process variation, Voltage, and Temperature. All of these affect the speed of the logic. \$\endgroup\$ – Elliot Alderson Apr 18 at 11:43
  • \$\begingroup\$ @ElliotAlderson sure it will be statistics, but it would be nice to have something like an MTBF as all I know only treats clock domain crossing. As user awjlogan says, PVT will have a strong influence on it, but an estimate of the worst case would be useful. That way I could justify my initial assumption that the system reset is long enough for all metastability to resolve, which was not completely off as user Mattman944 says. \$\endgroup\$ – njg Apr 18 at 12:46
  • \$\begingroup\$ Your previous comment is not consistent with your question. You said it was "crucial that all metastability has resolved" and asked about the time when the flip-flops "have to" resolve their state. You are asking for an upper bound in the question, not a 50% probability such as MTBF gives you. \$\endgroup\$ – Elliot Alderson Apr 18 at 14:44

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