After power up in an ASIC, is it save to assume that all flipflops are in a stable state ('0' or '1')? I do not care in which stable state they are, but it is crucial that all metastability has resolved. Adding resets would come at a high cost as these flipflops are part of a clock divider, where all the resets would need to be synchronised to intermediate clocks I do not use. Furthermore, all flipflops are T-flipflops. The time scale in which the flipflops have to resolve their state is in the order of milliseconds as all the power up circuitry like crystal has to start before.
I did read Output of a D flipflop upon power up?, but for me it is more the question about the timescale after which I can assume the flipflops to have resolved or how I could calculate it.