# How does the bootstrapping capacitor in this diagram operate

I am curious to know how the bootstrap capacitor Cbst in the following example charges up to Vcc + Vin?

According to my understanding, during the clock input which turns the low side mosfet ON, the Cbst is charged at Vcc via Dbst, during the next clock the low side mosfet turns off and the high side mosfet begins turning ON through Vcc via the emitter of the NPN buffer. This allows the drain voltage to reach the source of the mosfet which simultaneously passes through Cbst via the NPN buffer to the mosfet gate. When this happens the stored Vcc inside Cbst comes in series with the instantaneous mosfet source voltage, and together they execute the Vcc + Vin for turning ON the high side mosfet.

A brief clarification on this will be greatly appreciated!

• You got it! The only clarification I would make is that the top N-FET doesn't really care about the absolute voltage of the gate in order to turn on or off. It only cares about Vgs (voltage difference between gate and source). Because CBst is directly connected at the source of the FET, just think of the VCC stored in CBst being applied to the Vgs of the FET when the NPN turns on. – joribama Apr 19 '19 at 5:53
• Thanks for your reply, suppose the drain voltage is 110V, and Vcc = 12V, then what happens? Definitely the mosfet will not conduct the 110V with 12V Vgs alone! – Swagatam Majumdar Apr 19 '19 at 6:03
• Vg would be ~122V (after the FET turns on), but Vgs (Vg-Vs) would still be ~12V. The gate driving circuit sits on top of Vs. The level shifter circuit may become a little tricky in this case. Does it make sense? – joribama Apr 19 '19 at 6:37
• Yes I know it would be 122V, but how does that take place, how the 110 and 12 get in series, that's my question? – Swagatam Majumdar Apr 19 '19 at 8:20
• Right before the top FET turns on, Vs will be in some sort of transient, so the capacitor top voltage will be whatever the transient voltage is plus 12V. When the NPN turns on, the 12 V on CBst is applied directly to Vgs of the FET, which turns on as a consequence. Right after the top FET turns on it acts like a closed switch, therefore Vs=Vd=Vin=110V. Because CBst sits on top of Vs, the voltage at the positive side of CBst will be 110V+12V=122V. I hope it makes sense now. – joribama Apr 19 '19 at 9:01

$$\V_B\$$, is the boost voltage required for dual N-channel half-bridge switches. The high output side, (HO) Nch FET needs a gate voltage higher than Vdd to activate RdsOn. It generates this voltage from a charge pump using the LO side PWM high-frequency pulses. THe Cboot cap AC couples this signal then is cathode clamped to Vdd such that the pulses now ride above Vdd. Internal to the IC, they are then rectified by an internal diode Anode and small internal capacitance to create HO +ve pulses.

The +ve current discharge pulses are shown in blue to Q1 below, while the -ve charge pulses are pulled down by Q2 to 0V.

More details Ref: https://www.onsemi.com/pub/Collateral/AN-6076.pdf.pdf

• My estimate of Cb is >5x the Ciss of Q1, but there are more complex computations of ideal.
• It is also critical that Q2 has a good diode clamp to 0V to prevent -ve pulses on output Vs to load, so that it does not pull down the boost voltage Vs. This may occur by excessive effective series inductance (ESL) of Q2 source to ground layout.
• Thanks for replying, however I wanted the reply based on the diagram that I have provided because it does not depend on any specialized driver IC – Swagatam Majumdar Apr 19 '19 at 5:57
• Note: the schematic is just a logical connection and must never look like a big inductive loop as shown. Path lengths must be as short as possible to enclose the smallest area. for EMC reasons. – Tony Stewart Sunnyskyguy EE75 Apr 19 '19 at 6:05
• I am trying to follow your diagram but still cannot figure out how the drain voltage adds up with Vcc to become Vcc + Vd? – Swagatam Majumdar Apr 19 '19 at 8:23