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I attempted to build an 8-bit adder in Logisim by carefully chaining together a half-adder and 7 full adders, all made from basic logic gates. Unfortunately, it produced erroneous results; for example, 00000011 + 00000011 = 000000100 ! I found that the problem seems to occur around the half-adder and the least significant bit, so I tried to pinpoint it with a smaller, 2-bit adder:

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As you can see (unless I am going crazy), this one is off, too; s1 should also be lit! I can see why it's not lit; a0 and b0 produce a carry bit, which, along with a1 and b1 (or even if it DIDN'T carry), makes the XOR gate for s1 false. But from the book I am using, this should be the way to hook them up? What am I missing here?

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How does Logisim handle xor gates without exactly two inputs? A two-input xor gate should have an output which is true if one input is true and the other is false, but it's not completely unambiguous from just that description how that should be generalized to N inputs. The normal approach is to say that the output of an XOR gate of any size should be true if the number of "high" inputs is an odd number; I would consider any other meaning to be non-standard. Nonetheless, it's possible that Logisim is defining "xor(a,b,c)" as being "and(or(a,b,c), nand(a,b,c))" (meaning at least one, but not all, of the inputs is true). Split the 3-input xor into two cascaded two-input xor's and the circuit should behave normally.

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    \$\begingroup\$ According to this page, Logisim XOR is true if exactly one input is high, but you can change that behavior. \$\endgroup\$ – ughoavgfhw Oct 10 '12 at 23:37
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    \$\begingroup\$ @ughoavgfhw: Interesting. I know some people who avoid ever drawing an xor gate with any number of inputs other than two, but I don't know that I've ever seen an implementation where an xor gate with more than two inputs was high only if "exactly one" was set. Perhaps the xor gate symbol should contain a notation saying what it's outputting? \$\endgroup\$ – supercat Oct 10 '12 at 23:41

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