NOTE: This question is related to a homework project.
I’m designing a PA for the 850-880MHz band. We have quite a lot of freedom for doing that. Only two requirements are specified:
- The amplifier must reach P1dB=29dBm
- It must have at least 15dB gain at 1dB compression.
I expect some loss in the input and output matching networks, so to my mind, the device should reach at least P1dB = 30dBm and 16 or 17dB gain at compression. In this sense, I’ve chosen the following LDMOS device from NXP and downloaded its model for ADS.
I’m aware that this is a 3W device that far exceeds the project specifications, but I didn’t found a another suitable device with a nonlinear model freely available on the Internet. If you know a good source of nonlinear models for RF transistors, please let me know.
Well, I run a DC curve tracer simulation and selected the bias point so as to operate in class A or AB (VDS = 6.5V, IDS = 440mA). The IDS traces look like this:
Then, I’ve opened a design template: Design Guide→Amplifier→1 Tone Nonlinear Simulations→ Spectrum, Gain, HD, Power w/ PAE.
My problem is the following: I wanted to plot the loadline, so I put the time domain waveforms of IDS and VDS over the above DC traces. For my surprise, IDS takes negative values for a part of the cycle:
Then I examined the VGS waveform. I expected it would be a sinusoid since the gate is connected to a power AC source, but it isn’t. I simply can’t figure out why.
I’ve also checked out ATF511P8 from Avago. According to the datasheet, ATF511P8 should meet the specifications. Unfortunately, I discarded it because simulation shows that I need to increase the bias current far outside the maximum limits specified by the datasheet to meet P1dB=30dBm requirement. In this case, the loadline clips at IDS=0 for high drive level. Does this mean that the AFT05MS003N model is wrong?
So, my questions are:
- Why IDS takes negative values? Shouldn’t it be clipped to 0 instead? Is the device model still valid for the design?
- Why VGS is not sinusoidal?
- Does this mean that the results of the HB simulation are wrong?
Any advice will be welcome.
Thanks in advance.
EDIT As suggested, I've examined the loadline trace of a class C design. Specifically, this is a sample design that comes with the ADS. It can be reached from Design Guide->Amplifier->PA examples by class of operation->Class C->Spectrum, Gain, ...
As expected, the loadline is clipped at the bottom whereas the loadline of the AFT05 LDMOS describes an elliptical trace that goes below IDS = 0. Excuse my ignorance on the topic, but I've noticed that the active device on this example is a GaAs FET using the Statz model. On the other hand, I didn't find details about the AFT05 model, but probably it may be MET (1). I'll try to examine the loadline of another LDMOS device.