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I am studying Intel speed shift. I see a slide:

Reference

ss1

I don't understand, why the green line 1/f means system energy, I think more performance should need more energy as the red line (compute energy).

Original site: The Intel Skylake Mobile and Desktop Launch, with Architecture Analysis

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It looks like this graph attempts to explain how the energy per clock cycle typically behaves for a digital system. It is a bit stylized.

The green curve relates to power dissipation that is constant and doesn't change with clock frequency. ("system power" would then need to be understood as more or less constant leakages, quiescent currents, etc throughout the system). To go from power [J/s] to energy [J] per clock cycle you divide power by the clock frequency f [1/s]. For a constant power this gives a 1/f slope for the energy per cycle spent by static power dissipation.

For the red curve the exponents given for the "Compute power" seem like very rough estimates. Switching power is \$P_d \propto fC_LV^2_{DD}\$ for a constant load (switching every cycle). For higher clock frequencies the supply voltage is scaled up as a higher voltage is necessary to speed up the digital switching - enough to support the higher frequencies. However the speed-up you get is typically better than linear with \$V_{DD}\$, so \$P_d \propto f^a\$ with \$a\$ somewhere a bit above 2 is more likely in my opinion, although \$P_d\$ can be dragged up by other leakage contributions which show a supply voltage dependence (leakage, short-circuit leakage, etc.).

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  • \$\begingroup\$ question, take power [J/s] to energy [J] per clock cycle, why divide power by the clock frequency f? why not divide power by period T (1/f )? \$\endgroup\$ – Mark Apr 22 at 8:36
  • \$\begingroup\$ @Mark Dividing by the clock frequency (1/T) would be the same as multiplying with the clock period (T). \$\endgroup\$ – HKOB Apr 22 at 17:36
  • \$\begingroup\$ energy (J) = power x time; energy (J) / per clock cycle = power x time / per clock cycle = power x time / T ==> energy (J)/per clock cycle = power x time x f, isn't it ? \$\endgroup\$ – Mark Apr 23 at 3:06
  • \$\begingroup\$ Energy is the integral of power with respect to time. When you assume an average constant power the 1st part is correct (maybe your understanding in the rest is correct but I couldn't read it). So to get the graph above one would find an average power over many clock cycles and then multiply by T to get the average energy. \$\endgroup\$ – HKOB Apr 23 at 6:48
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Power Management

ss1

That diagram is in the section of the slidedeck where they're talking about power management is stating that the energy efficiency for System's on a Chip (SoC) will behave inversely proportional to the frequency of the CPU as it increases. Power spectral density is inversely proportional to the frequency of the signal.

This diagram might help illustrate this effect a bit more:

ss2

Imagine that as the CPU's over frequency increases, or as frequencies of the RAM or various busses increase, the amount of power available to leverage will be in a relationship that will be most like the graphic showing the frequency domain (lower right).

  • NOTE1: the relationship of 1/f is very common in nature and is typically called fractal noise" or "pink noise".
  • NOTE2: This is also why Fourier transforms are important in our field.

Additional details

The main author of the slidedeck you reference, Efraim Rotem, also wrote this paper titled: H-EARtH: Heterogeneous Multicore Platform Energy Management.

In this paper he mentions this:

Platform components consume fixed runtime power with energy proportional to runtime (1/f). All other components are ignored. The two opposite energy trends might have a global minimum (see Figure 1).

References

These are helpful in understanding many of the concepts that are key to grasping all this.

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  • \$\begingroup\$ sorry, I still can't get it. The green line means SoC and system energy(power consumption?), does it mean higher frequency will consume lower power ? \$\endgroup\$ – Mark Apr 22 at 3:16
  • \$\begingroup\$ @Mark - no it means as the CPU freq. increases the power available with SoC must decrease and that its relationship is equivalent to 1/f. They're trying to say that in order to realize these higher freqs they have less power available to deal w/ noise within the system, and must adhere to this 1/f relationship when dealing w/ it. \$\endgroup\$ – slm Apr 22 at 3:24
  • \$\begingroup\$ @Mark - this slidedeck is unfortunate b/c the phrase - "closing system power" shows up no where except in this deck. They're taking liberties in how they're explaining this to make a point about SoC, higher frequencies, and the mgmt of power within these systems. \$\endgroup\$ – slm Apr 22 at 3:26
  • \$\begingroup\$ @Mark - the phrase "closing system power" and the fact that these are in the "Power Management View" portion of the deck are suppose to illustrate what they need to do to meet the demands going forward to realize these higher freq CPUs. This is unnecessarily being clever IMO. \$\endgroup\$ – slm Apr 22 at 3:28
  • \$\begingroup\$ @Mark - with non-SOC lower freq tech we had the luxury of making them noisy and using a lot of power to make it all work, As power available has gone down - 5V -> 3.3V -> 2.5V -> 1.8V - we've had to consolidate components (SoC) and deal w/ less power, yet still deliver on higher freq. If you plotted this it would mimic the 1/f curve. \$\endgroup\$ – slm Apr 22 at 3:33
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The platform energy is proportional to the run time of the workload and therefore inversely proportional to CPU frequency.

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