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I know we can route microstrips on top of both ground and power planes, but can we use Grounded coplanar in this arrangement?

  • bottom is GND
  • In top layer we have one GND and a PWR.
  • All gaps are 0.15mm
  • Working frequency: 12GHz

enter image description here

1.Will it damage integrity of signal? Why?

2.(The question has been added refering to marcus mullers comments) I've used this design because Analog Devices has used it on his own reference design. But will it advantageous since the field will confine in between two microstrip. (I think it helps at least to prevent field to propagate through PCB material.) And will Differential GCPW cost of design worth it to switch to it from simple microstrip?

Analog devices reference design:

1.UG-864: enter image description here

2.UG-866: enter image description here

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  • \$\begingroup\$ Is there ground below it? I don't see that! \$\endgroup\$ – Marcus Müller Apr 20 at 8:16
  • \$\begingroup\$ also, differential lines are typically not done as coplanar to a ground plane on the same layer – that makes little sense, as the electrical field is supposed to be dominantly between the two differential conductors. Which design tool gave you this geometry? It looks like the ground planes are as close as the two conductors, and that makes little sense, unless you want to build an impedance matching, lossy network, not a transmission line. \$\endgroup\$ – Marcus Müller Apr 20 at 8:18
  • \$\begingroup\$ So, the question is: Why are you adding this top layer ground plane so close to the transmission line? Is that the result of an electromagnetic simulation, or from some design tool, or did you just, like in your previous question "read somewhere" that coplanar is good and then forgot that you design transmission lines for a specific impedance, and putting ground close to it changes that impedance? \$\endgroup\$ – Marcus Müller Apr 20 at 8:21
  • \$\begingroup\$ In fact, since I already answered the question "do I want coplanar ground plane in differential grounded microstrip" in that question, and you accepted it: As said, don't add the coplanar ground, it distorts everything. This is 100% a duplicate. \$\endgroup\$ – Marcus Müller Apr 20 at 8:23
  • \$\begingroup\$ Duplicate of: electronics.stackexchange.com/questions/415668/… \$\endgroup\$ – Marcus Müller Apr 20 at 8:23
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My main concern would be that each VCC via will produce an antipad in the ground plane, making the geometry asymmetric.

Ideally the traces in the differential pair only interact with each other, as another answer said. But practically (especially in a dense design like your example), they also interact with surrounding conductors, and the coplanar ground, or ground beneath a differential microstrip will affect the characteristic impedance. And discontinuities in the ground will cause reflections and/or mode conversion in the propagating signals.

So one trace having ground directly beneath it, and the other having ground with periodic gaps due to the VCC vias, is likely to produce undesirable results, such as a different characteristic impedance than expected or differential-to-single-ended signal conversion.

I'd try to find an alternative geometry. Either differential microstrip, or coplanar with ground on both sides.

I believe both of the examples you showed from Analog Devices documentation show CPWG with ground on both sides. Neither one shows a power net being used as ground like you propose.

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As long as it's properly decoupled, power counts as ground, as far as RF and microwave signals are concerned.

With CPW, it needs a bit more thought to 'properly decouple' it for RF. In classic CPW, where you'd bridge the two grounds with a link to keep the grounds balanced, you'd bridge with a small ceramic capacitor. Note that the normally many μF power decoupling capacitors will not do this job, but of course you still need them in their normal positions to decouple the power for you.

Where you've annotated the 0.2mm gap at the top of your picture, you'd put a 100pF or so (depending on signal frequency, bigger for lower frequencies, at 12GHz 10pF is about 1 ohm, you'll have more series impedance from the physical length of the cap than its capacitance) across this gap. You'd need another one in a similar position at the signal destination.

These caps to ground will still allow a small amount of signal to excite the power track with respect to the ground plane. If the length of power line between these two caps is an unfortunate length, and resonates with your signal or harmonics in it, then you'll need to nail it to ground at intervals with additional small caps, with a much-sub-wavelength spacing.

At 12GHz, it will be very difficult to get your physical capacitor length down far enough to be a really good ground. It may be better to put series RCs between power and ground to sap energy from the resonance to tame it, rather than trying to kill it.

One of the main reasons for going to CPW is if the IC you're interfacing with has pins that suit it, like GND-sig-sig*-GND. This one doesn't, it's GND-sig-sig*-AVDD. It would be far less complicated to exit the IC differentially on sig-sig* and run differential microstrip. Or if you want to run CPW a long way from the device, via the AVDD to get it out of the way, and run your CPW between real grounds.

Don't forget that if your sig-sig* are balanced as they leave the IC, there are no signal currents flowing to ground anyway. If you want to introduce a ground, that's your choice for when you let the signals see some ground, rather than seeing their complements.

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  • \$\begingroup\$ Thx for answer. 1.You mean: ordinarily, I need two caps, one in transmitter and the other be in receiver side. But I must care because I need to place the caps repeatedly every (for example) 1/8 lambda? 2.Will the 100pF be enough for 12GHz? 3. Do you think using of GCPW for differential being useful?(I think it must be usefull since it confines the fields and prevent them to propagate them through PCB substrate) \$\endgroup\$ – mohammadsdtmnd Apr 20 at 11:54
  • \$\begingroup\$ I think your answer is 90% of my question but if you could complete your answer referring to my comment and updated question, I will accepted your answer safely, thank you so much. \$\endgroup\$ – mohammadsdtmnd Apr 20 at 12:04
  • \$\begingroup\$ @mohammadsdtmnd I've update my answer, but I don't think you're going to like it. \$\endgroup\$ – Neil_UK Apr 20 at 13:03
  • \$\begingroup\$ OP probably didn't "annnotate" the 0.2 mm gaps. His design tool is telling him he's violating a design rule requiring 0.2 mm or greater gaps between vias. \$\endgroup\$ – The Photon Apr 20 at 14:29
  • \$\begingroup\$ Wholeheartedly thanks for your experience sharing and I had loved your answer, you didn't take into account the anti-pad and this is what make this geometry impossible to realize. But you've provided ideal solution for this geometry and it's inspiring, and thank you. +1,Still I think mix of your answer two are my answer, you answer has more weight but that is the final shot. \$\endgroup\$ – mohammadsdtmnd Apr 20 at 14:57

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