Before explaining i should point out that i refer to changes of signals in the text as a reference change on which i will calculate these times as 50% change of one signal to 50% change of the other on the time axis. I am simply trying to find that reference change on which that time is calculated.

I'm trying to calculate the setup and hold time of this edge-triggered d flip flip using simulations in Pspice but am having troubles in deciding what those times represent in the graphs of the simulations.

In my class notes (which this is the exercise for) it says that the hold time is calculated from the output of the first inverter to the output of the second inverter, and the setup time from the input D to the output of the first inverter.

For simplicity let's say that the outputs in order are A,B,C,D,Q

When calculating the hold time, when CLK=0, B is kept on VDD until both A and CLK are on VDD. That change when B is discharging from VDD to 0 is what should be the reference change for calculating the hold time. That would be the ammount of time it takes for B to pass the information to the other inverter as it can only change once during CLK=VDD. The only way i found to calculate this is when i make CLK=0 and during that time i change D from VDD to 0 to change A from 0 to VDD and observe the discharge as time when CLK=0.5VDD (starts rising) to time time when B=0.5VDD (starts discharging)

The other way, having CLK=VDD and changing A from 0 to VDD i couldn't make happen because CLK in the first inverter interferes even though my class notes say that it is the change from A to B. So i don't know whether this is ok.

Could the first way be used to calculate the hold time?

For the setup time, it should just be the change in A from 0 to VDD so that would be the change of D from VDD to 0 while CLK=0 right?

Edge-Trigerred D FF


1 Answer 1


I'm writing this answer just in case someone really wants to characterize the setup/hold times of a flip-flop, rather than answer a homework question.

There isn't really a sharp pass/fail boundary that you can use to define setup and hold time. As the changing edge on the data input gets closer to the clock edge (either before or after) you will see that the delay from the clock edge to valid Q output starts to increase. The flip-flop will fail because the clock-to-Q delay becomes unacceptably large, not because it fails to change states entirely.

So, you first need to determine that maximum clock-to-Q delay, by simulating with very large setup and hold times, over the range of temperature, supply voltage, and process variation.

Now you must decide what maximum value of clock-to-Q delay you want to specify for your flip-flop.

Then you run simulations, again over PVT, slowly moving the data input edge closer to the clock edge until the measured clock-to-Q delay exceeds your maximum specified value...at that point, the time from the data edge to the clock edge becomes your required setup time. A similar approach is used to find the hold time.


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