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Let me define:

  • Branch delay slot: Typically assemblers reorder instructions to move some instructions immediately after branch instruction, such that the moved instruction will always be executed, regardless whether branch is taken or not, without leaving the system in inconsistent state.

  • Branch prediction prefetch: predicting what will be the outcome of branching condition and then prefetching instructions from the resultant location, so that they will be immediately executed after branch instruction.

Now, lets consider below execution sequence (below, F: instruction Fetch, D: instruction Decode, X: eXecute, M: Memory access, W: Write back):

BRANCH   F   D   X   M   W
INSTR1       F   D   X   M   W
INSTR2           F   D   X   M   W
INSTR3               F   D   X   M   W

Usually branch condition is evaluated and executed in X stage. By this stage, INSTR1 and INSTR2 are already started and these are the instructions which can be affected by out choice of whether to use branch delay slots or branch prediction prefetch or both. I did not find any text to discuss this clearly. SO I tried to guess it as below:

  • When we use both, then instruction sequence would be:

    BRANCH: branch-instruction
    INSTR1: branch-delay-slot
    INSTR2: branch-prediction-prefetch
    
  • When we use only branch prediction, then instruction sequence would be:

    BRANCH: branch-instruction
    INSTR1: branch-prediction-prefetch-1
    INSTR2: branch-prediction-prefetch-2
    
  • When we use only branch delay slots, then instruction sequence would be:

    BRANCH: branch-instruction
    INSTR1: branch-delay-slot-1
    INSTR2: branch-delay-slot-2
    

Am I correct with this? Is it how this happen actually for different cases? Or there are some more details?

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  • \$\begingroup\$ I don't grok the "When we use only branch" sequence: how can it have brach-delay-slots? Also, showing the piece of assembler you seem to have in your header would be clarifying. \$\endgroup\$ – Wouter van Ooijen Apr 21 at 16:18
  • \$\begingroup\$ (1) "I don't grok the "When we use only branch" sequence: how can it have brach-delay-slots?"- fixed the sentence, I accidentally left it incomplete. Hope it makes sense now. (2) Didnt get this: "Also, showing the piece of assembler you seem to have in your header would be clarifying." Do you mean to say, I should specify the assembler I am working with? If yes: I am reading pipelining chapter from the book "Computer Organization and Design" by Patterson. So dealing with pure theory and solving exercise problems. \$\endgroup\$ – anir Apr 21 at 16:40
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Yes, that could be what would happen, although I don't recall any architecture that combined prediction and delay slots: if you have prediction, it can run (lookup in a small memory) in parallel with the execution step, so no delay slots would be needed.

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  • \$\begingroup\$ thanks to confirm, because such scenarios are covered in the exercise problems of Computer Architecture book by Patterson. It gives direct solutions without giving any explanation. Neither the chapter contents discuss this. \$\endgroup\$ – anir Apr 22 at 17:58

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