My university resources say that DMA transfers the bunch of data from IO unit to memory or vice verse when processor is not busy with data and address bus. According to the resources, DMA Controller needs these two system bus for data transfer, and it cannot perform data transfer when they are used by processor.

Up to now, It makes sense.

My university resources also says that DMA transfers the data in some instruction cycle steps in which processor does not use data and address bus. For example, an instruction cycle consists of 4 steps:

1) Instruction Fetch
2) Instruction Decode
3) Operand Fetch
4) Execution

DMA transfers the data when processor works in Instruction Decode or Execution, since CPU will not use address and data bus. In this point, I am confused.

Modern processors utilize instruction pipeline. In other words, the instructions are not executed sequentially. When command 2 is in "instruction decode" section, command 3 is in "instruction fetch". The instructions follow themselves without any gap. In this case, there will be always an instruction in the step "Instruction Fetch" or "Operand Fetch". Namely, data bus and address will be always used. DMA cannot find a chance to benefit from these bus lines for data transfer. Instruction pipeline does not allow DMA to be used.

How and when is DMA used ? I explained my confusion below. Is there anyone who can explain this ? My university resources are wrong or there is a trick that I cannot figure out ?

  • \$\begingroup\$ Which "University resources"? What processor architecture were they discussing? Which "modern processor" architectures are you thinking of or want to know about? Narrowing this down to a specific architecture will make it much easier to give an answer within the scope of the site. (i.e. not have to write you a whole book) \$\endgroup\$ – The Photon Apr 21 '19 at 14:57
  • \$\begingroup\$ The DMA controller will occupy the bus when it needs to, potentially excluding other accesses (CPU,...) during that time. So, in case the CPU would require 100% of the bus to operate at full speed, it would be stalled intermittently by the DMA. \$\endgroup\$ – JimmyB Apr 21 '19 at 15:03
  • \$\begingroup\$ DMA is not a single thing nor is the concept static over time as changes have occurred. I remember DMA from 50 years ago and I used DMA just a few years ago. No similarities and they operated at different places in the systems. In the P II (where I'm most familiar) there was no DMA until you got to the South Bridge supporting the old ISA bus (very slow.) PCI didn't support it, only bursts but not DMA, per se. The front side bus didn't support it. And the L1 cache took 3 clocks, the L2 cache (backside bus) took 6 clocks, etc. No DMA. Just be aware there is no single answer. Context matters. \$\endgroup\$ – jonk Apr 21 '19 at 15:30
  • \$\begingroup\$ In some systems, DMA will override the processor so the processor can't do anything (except from cache) until the DMA is done. \$\endgroup\$ – user253751 Jun 14 '19 at 0:32

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