My university resources say that DMA transfers the bunch of data from IO unit to memory or vice verse when processor is not busy with data and address bus. According to the resources, DMA Controller needs these two system bus for data transfer, and it cannot perform data transfer when they are used by processor.
Up to now, It makes sense.
My university resources also says that DMA transfers the data in some instruction cycle steps in which processor does not use data and address bus. For example, an instruction cycle consists of 4 steps:
1) Instruction Fetch 2) Instruction Decode 3) Operand Fetch 4) Execution
DMA transfers the data when processor works in Instruction Decode or Execution, since CPU will not use address and data bus.
In this point, I am confused.
Modern processors utilize instruction pipeline. In other words, the instructions are not executed sequentially. When command 2 is in "instruction decode" section, command 3 is in "instruction fetch". The instructions follow themselves without any gap. In this case, there will be always an instruction in the step "Instruction Fetch" or "Operand Fetch". Namely, data bus and address will be always used. DMA cannot find a chance to benefit from these bus lines for data transfer. Instruction pipeline does not allow DMA to be used.
How and when is DMA used ? I explained my confusion below. Is there anyone who can explain this ? My university resources are wrong or there is a trick that I cannot figure out ?