There are simpler answers, but incomplete, so challenge yourself to understand and ask better questions. This is just a supplement to @analogsystemsrf fine answer.
There must be a DC bias for the inverter and it must be self-biased with this negative feedback to allow it to operate with max. the gain in the linear mode.
Since this question suggests a design using the inverting parallel resonant crystals, (Xtal) the CMOS inverter creates the gain-phase condition required to sustain oscillation by AC positive feedback.
doesn't the quartz oscillator have to oscillate at the same frequency as the AC?
It does not mean you get 5kV out of the crystal with 1V input because the gain is limited by the damping of the ESD input clamp diodes. Due to XTAL power limits of 10uW, a driver Rs of 1k is often mandatory for best MTBF.
Crystals > 20 MHz tend to operate as harmonic oscillators 3rd 5th or 7th harmonics called "overtones".
Anecdotal: I used this fact to design an injection locked Xtal Oscillator that required only 10 clk cycles then no data transitions for 1024 NRZ data bits at 4Mbps to self-clock synchronous-data with no need for bi-phase or a separate clock signal to be transmitted. This was broadcast on TV in the early '80s using blanking interval lines to download games etc to home computers such as ][+, Commodore and TRS-80. Sadly ahead of it's time for slow decision makers in Cable TV to buy our network design.