# How can I detect that a ZVD-style 'backpower protection circuit' is operating correctly?

I'm designing a circuit that needs a 'backpower protection circuit', similar to what the Raspberry Pi HATs use. This is meant to block voltage from the secondary board when the primary board is supplying voltage: I've prototyped this in CircuitLab using other jellybean parts, and put some oscillating power supplies in place so I can see how it behaves: simulate this circuit – Schematic created using CircuitLab

However, even when simulating the circuit, I don't see it supplying the max(v1,v2) that I'd expect to R4, which is my simulated load.

Assuming the circuit is correct, how would I measure that the correct voltage is being sourced or sinked to the right side of the circuit? How could I show which "direction" it is coming from? (such as by an LED)

• Use R3 as a current sense resistor and measure the polarity of the voltage across it. – DKNguyen Apr 21 at 19:16
• Lots of problems with your schematic for simulation. Perhaps the most pronounced problem is $V_2$. Another is the body diode in the FET in the case where $V_2$ is active. In any case, why not just use a 555? It includes two comparators, where one of them has priority over the other. Not only that, the discharge pin can be used for your LED indicator, as well. The OUT pin would select which of the two supplies is bypassed to the switched power wire. The supply to the 555 comes via both rails through low reverse leakage diodes, so whichever is higher supplies the 555. – jonk Apr 21 at 22:18

## 1 Answer

The circuit is correct, but your problem is only that the design parameters are not-defined for Vt, gm, β,Rs,Rc or RdsOn and thus the wrong load was used to simulate a power supply.

Here I chose gm = 5 A/V above threshold with Vt = -2 V

With high impedance ratios for gain of Rc/Rs the FET starts conducting with a forward voltage of about 2% of the Gate threshold voltage. High values of collector R achieve a high differential voltage gain on the FET using the battery voltage to bias the FET and the ratio values on the PNP collectors of 1:5 yet very high ratios relative to battery impedance to reduce the reverse current to 10nA.