I made a t flip flop using structural modeling in verilog.
module Tflip(input T,input clk,output Q,output Qbar) ; wire S,R; and(R,Qbar,T,clk); and(S,Q,T,clk); SRLatch srt(S,R,Q,Qbar); endmodule module SRLatch(input S,input R, output Q, output Qbar); nand(Q,R,Qbar); nand(Qbar,S,Q); endmodule
And then I tried to make T flip-flop in behavioural modelling. It took me ages to find a neat way to initialise the flip-flop.The below code works great. Is it always required to use a reset of some kind ? Would that make the structural code above wrong?
module T_FF(input T,input rst,input clk,output reg Q); always@(posedge clk) begin if (rst == 1) Q <= 0; else if (T) Q <= !Q; end endmodule
I tried to implement a version without a reset signal, but it would only work if the test bench started off a certain way.
Every diagram of T flip-flop i looked for did not show a reset signal, so it took me a lot of time to even understand a reset input was required. It feels like structural modelling a foolproof way of creating things.