In the JEDEC LPDDR4 spec it is mentioned that LPDDR4 DRAM can support burst length 32(BL32) and also the LPDDR4 DRAM architecture is 16n prefetch. I want to know how burst length 32 be possible with 16n pre-fetch.
Let's take only one Data macro i.e DQ[7:0] (x8) for read transaction. Burst length 32 means DRAM sends 32*8bits(256 bits) of data for one read transaction. For one read request, DRAM internally pre-fetchs 16n(16*8 = 128 bits) data into its buffer and transmits on to read DQ along with DQS.
My question is how the DRAM sends 256 bits of read data if it prefetchs only 128 bits?
Please clarify my question.