9
\$\begingroup\$

I can´t seem to grasp this, what is the difference between superscalar and a multi-core processor?

I keep mixing them up, so some simple points on what they do would be great.

\$\endgroup\$
13
\$\begingroup\$

Super-scalar processors means that you dispatch multiple instructions during a single clock cycle. The reason this is differentiated from multi-core is that you only get one instruction counter. So you keep track of multiple instructions in-flight, but all the instructions are from a single program. This is still just one process. Now I said "you get one instruction counter," and technically that's true in that there is no point in which your code will experience a disparity except using some branch prediction schemes (Speculative Execution: you simultaneously execute both branches and throw away the "wrong" prediction's result).

When you get into multi-core you have multiple instruction streams executing simultaneously. The important part is that each core (executing with its own instruction counter) can also be super-scalar in order to execute each single process more quickly!

It is possible to have super-scalar without pipelining or out-of-order execution by having what's called very long instruction word or "VLIW". This is also called "static" super-scalar (i.e. it's in the code itself). This is where you basically have enough components to execute multiple instructions at the same time, and you fetch multiple instructions at once and then run them. In its most simple form, imagine that you said "this processor will always fetch and execute two instructions at the same time." Then as long as the coder could find work to be done simultaneously in the same process, you would double your throughput! If you couldn't find two instructions to put together, you would simply pair one instruction and a NOP. This idea is not very good mostly because if you make a better version of the processor which can execute 3, 4, or more instructions at the same time, all your old code breaks! But they solved this in a quite ingenious way, you should check out explicitly parallel instruction computing or "EPIC" stuff if you want to know more.

Dynamic super-scalar with pipelining can take advantage of both data-independent instructions as well as instruction-level parallelism, which is what makes it such a powerful combination. Essentially it allows you, with enough hardware, to execute as many independent instructions simultaneously as possible.

Dynamic super-scalar with pipelining and out-of-order execution was essentially the limit of instruction-level parallelism: you would try and execute multiple instructions in the same stage simultaneously, trying to find operations which operated without data dependencies. You could finish out of order, you would start out of order, there are all sorts of things you need to do to keep your head on straight while doing super-scalar stuff. Multi-core says "hey programmer! Give me multiple problems I can solve at the same time!" and then since the programmer is capable of seeing independently solvable problems beyond just a few lines apart in the compiled assembly, they can more efficiently program those solutions for multi-core.

Super-scalar isn't even capable of solving problems like "how do I execute these two programs more quickly." It could only execute each independent program faster.

Hope that helps, sorry if it's a bit disjointed.

--Edit--

Modified to take into account ajs410's point that I had confused multiple ideas.

\$\endgroup\$
  • \$\begingroup\$ Yeah, that made it a lot clearer, thank you! By the way, I think the word you´re looking for i "Speculative Execution". Anyway, thanks again. \$\endgroup\$ – marsrover Oct 12 '12 at 8:57
  • 1
    \$\begingroup\$ To make things clarified by @KitScuzz a bit more complicated again, also read HyperThreading \$\endgroup\$ – ppeterka Oct 12 '12 at 9:31
  • \$\begingroup\$ I think this blurs super-scalar, out-of-order, and pipelining. Specifically, super-scalar says "I have four ALUs, so I can grab these four add instructions (from a single thread!) and issue them during the same clock cycle." Out-of-order execution rearranges the instruction stream around data dependencies to maximize instruction-level-parallelism. Pipelining will issue new instructions while the old instructions are in-flight. Out-of-order execution and pipelining have a strong synergy with superscalar execution, but are not strictly required to satisfy the defintion. \$\endgroup\$ – ajs410 Oct 12 '12 at 18:50
  • \$\begingroup\$ Fixed! Sorry for the delay. \$\endgroup\$ – Kit Scuzz Oct 21 '12 at 20:22
0
\$\begingroup\$

If you look back to earlier processors like the 80486 or Pentium then a CPU was a single logical unit of processing. It executes a single stream of instructions at a time. A single CPU was also a single silicon chip. If you wanted more processing power then you might buy an expensive server motherboard that had slots to fit two separate CPU's. Then you had a two CPU machine and so two processing cores.

At some point Moore's Law meant we had so many transistors available in the silicon that you could place all the circuitry for two CPU's into just a single chip. Now you have the potential for naming confusion. Saying you have two CPU's could mean you have the older style two silicon packages or the newer single silicon package but with the processing setup of two processors. To resolve this we now mean CPU to be a single silicon package and a Core is a single logical processing unit within it.

Super-scalar refers to a technique used within a core to try and improve performance and allow it to process more instructions per cycle on average. A scalar processor executes at most one instruction per cycle, super-scalar means it can potentially execute more than one instruction per cycle. For example, if the processor has a functional unit for integer arithmetic and another for floating point then why not use both at the same time to execute two instructions simultaneously. What if you have three integer units and two floating point units? Now you have even greater potential for parallel execution. But you also need more transistors for the implementation and far more complicated logic to make it work reliably. In the real world you tend to get super-scalar used in conjunction with out-of-order designs because they compliment each other.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.