I am using the Altera Quartus II software to compile Verilog for a Cyclone IV FPGA. In my case, the FPGA is fixed; I cannot get a faster one.
Now one isolated module in my design, which deals with relatively fast clocks, is not meeting timing. I have spent some time trying to simply the code, and understand how the compiler interpreted my code with the "RLT viewer" and "Technology Map Viewer".
Despite that, my design is still not meeting timing by a little. What should I do? Are specific techniques/tricks I can try? Can I ask Quartus II to really try its best to optimize the specific module?