I like to consider myself fairly experienced in Electronics Design, but upon being contracted to review this schematic I'm a little stumped. This is basically the output stage of a boost power supply:

enter image description here

I've drawn in the red lines to symbolise where the power actually flows. The MOSFET Q2 on the top left makes sense (although there is no base resistor for Q3, which is the first mistake I pointed out. 3.3V from a micro directly to a 0.7V base-emitter diode, youch!). This is just a P-FET power switch.

What's weirder, but, is after this - the Q4/Q5 pair. Q4 is another P-doped transistor acting as a switch, but the net driving its base in Q5 - and what's driving Q5? The output of Q4! It's a paradox if you ask me. There are two main concerns from me:

  1. The first is, what's the actual point of this? The only thing I can think of is, assuming Q4 (and thus Q5) turns on by "default" if the output +Vout is shorted to GND, this turns off Q5, which turns off Q4, which disconnects the output voltage from shorting directly to said GND. Fair enough, if this is what it's for - if it's not though, please do correct me?
  2. The second is, removing my assumption, will this even turn on in the first place? If Q4 was a depletion mode P-MOSFET, I would say yes as this would be "on" by default, let 12V flow through in the "initial" state, and then turn on Q5 until the output +Vout was shorted to GND. In this case, but, this is just a plain-old PNP BJT which, unless I'm crazy, is "off" by default. Thus, it won't ever turn on.

Thanks. Any insight from people would be great, as it seems like a handy little tool for preventing short-circuit overcurrent (although these days, this sort of protection is built into a lot of chips internally). But it looks to me like it hasn't quite been executed correctly, and it needs to be a depletion mode MOSFET there instead so it at least has a defined initial state.

  • 2
    \$\begingroup\$ Q4 and Q5 do not make sense in this circuit. They are in a SCR topology so +Vout has to be ON first. Very odd design. \$\endgroup\$
    – user105652
    Apr 24, 2019 at 3:39
  • \$\begingroup\$ A blown-fuse indicator? \$\endgroup\$ Apr 24, 2019 at 3:41
  • \$\begingroup\$ @Sparky256 Great, glad you agree with me. I was also thinking having a BJT in the direct power path is probably not the best either due to saturation voltage across CE. You have a crap ~0.2V drop in the expected output (could be critical for some applications) and a VI power loss there. Low Rds(on) MOSFET would be better even just for that sake. \$\endgroup\$
    – DSWG
    Apr 24, 2019 at 3:41
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    \$\begingroup\$ @sstobbe I've used those in heaps of FPGA designs and can confirm the part number they've prescribed for Q3 is not one of those. Think I'm just dealing with low quality design here. \$\endgroup\$
    – DSWG
    Apr 24, 2019 at 3:45
  • 1
    \$\begingroup\$ The SCR might be intended as a crowbar to blow the fuse, but then I wonder what values of R16/R17 would make sense for that. \$\endgroup\$
    – CL.
    Apr 24, 2019 at 7:07

1 Answer 1


Behavior :

The circuit is a latch.

Assuming the starting voltage across C5 is 0V and Q2 is on, Vbe of Q5 is 0V and will stay that way, unless some other (unshown) part of the circuit pulls up the voltage of the +Vout net, turning on Q5 and then Q4.

From there, I see two possible answers :

  • This is a strange way of activating an output from somewhere else, which is overcomplicated;

  • This is bad design

I (and all the commenters) would favor the second theory, which is confirmed by a few other elements, like the lack of a base resistor on on Q3 or filtering globally.

In Conclusion, check the rest of the schematic for something that could boostrap +Vout, or other examples of copy-pasted circuits that do not belong.

  • \$\begingroup\$ +1 for a rational answer to an irrational circuit. \$\endgroup\$
    – user105652
    May 2, 2019 at 23:51

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