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I need to use 8 kHz as a clock signal for my LFSR IP core in my block design. But this low rate can not be implemented in ARTY 7 , as shown in the attached picture !

What are the other choices I have in order to achieve the output of LFSR at the low rate that I want ?

I read about delays in FPGA , but I found delays are not synthesized in FPGA !

Looking for your help,

Thanks clocking wizard in Vivado

Edit : I added enable signal (i_en) , which is controlled by a counter. As shown in my code below:

    -- Library's
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LFSR3 is
   Port (
      i_clk           : in  std_logic;
      o_lsfr          : out std_logic_vector (2 downto 0)
     -- i_en            : in  std_logic
    );
end LFSR3;




architecture Behavioral of LFSR3 is

signal i_en    : std_logic := '1';
signal r_lfsr   : std_logic_vector(2 downto 0) := "100";
constant maxcount  : integer := 625;
signal counter :  unsigned(9 downto 0) := to_unsigned(0, 10);


begin

  o_lsfr <= r_lfsr;

  LFSR_proc: process(i_clk)
   begin
    counter <= (others => '0');
    i_en <= not i_en;
    if (i_en = '1') then
       if(rising_edge(i_clk)) then


          r_lfsr(2) <= r_lfsr(0) xor r_lfsr(1);
          r_lfsr(1) <= r_lfsr(2);
          r_lfsr(0) <= r_lfsr(1);
       end if;

    else
    -- line 75 (the error)
      freq_8kHz: while (counter <= maxcount) loop
          counter <= counter + 1;
       end loop freq_8kHz;
   end if;     
  end process LFSR_proc;

end Behavioral;

And , when I run synthesized an error appeared :

"[Synth 8-3380] loop condition does not converge after 2000 iterations ["d:/Users/dell/Vivado_projects/LFSR2/LFSR2.srcs/sources_1/bd/LFSR/ipshared/4f95/src/LFSR3.vhd:75]"

I have pointed to the error location in my code (line 75) . So plz , could you tell me why my loop seems to be infinite (does not converge) !?

Thanks.

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  • 6
    \$\begingroup\$ You should probably be using an infrequent clock enable rather than such a slow clock. It may also be that your application doesn't really call for implementation in dedicated FPGA fabric, but would belong better in software running either in an internal soft-core processor, or in an external or internal had core. \$\endgroup\$ – Chris Stratton Apr 24 '19 at 20:48
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Chris is right that clock enables are considered best practice, but if you want a slow clock anyway, you could use a manual clock divider like the following:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clkdiv is
    port (
        clki : in std_logic;
        divider : in unsigned(31 downto 0);
        clko : out std_logic := '0'
    );
end entity clkdiv;
architecture rtl of clkdiv is
    signal count : unsigned(31 downto 0) := (others => '0');
begin
    process (clki)
    begin
        if rising_edge(clki) then
            if (count = divider) then
                count <= (others => '0');
                clko <= not(clko);
            else
                count <= count + 1;
            end if;
        end if;
    end process;
end rtl;
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