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Im doing a design with a implementation of 1Gb ethernet switch, for that I bought a evaluation board to do it well.

The problem is that in the layout of the ev board I can check that the track impedance used to link the output of the chip (which has the PHY interface integrated) to the RJ45 connector is different than the right one which is suposed to be 100ohms as many routing guidelines for Ethernet say.

Here is the impedance calculation. (the values ​​are taken from the layer stack and the design of the PCB that are included in the documentation associated with the user manual)

enter image description here

And here is the datasheet of the evaluation board that Im using:

http://ww1.microchip.com/downloads/en/devicedoc/50002587a.pdf

Any idea why the differential impedance (83,73ohm) is so far from the ideal 100ohms recommended in ethernet routing?

thank you all!

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  • \$\begingroup\$ The real test would be a measurement of the physical impedance of the track. \$\endgroup\$ – pjc50 Apr 25 at 15:59
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Using exactly the same values as you did, but with another calculator (from EEWeb), I get:

enter image description here

Which is different from what you had, and closer to the target. There are several models that can be used to estimate the differential impedance, and different tools may use different underlying computation techniques, so you can get different results.

In any case, 83 is within 20% of the ideal 100 ohms value, so you're in the right ballpark. If you need tighter tolerances anyway, you would need to ask the PCB fab house for impedance control, which implies that the fab house itself adjusts your layout (trace width / separation), according to the characteristics of their materials and fabrication process. So you don't have to worry about relying on the results of a random PCB calculator tool: instead, you specify the target impedance to the PCB fab house and they take care of it, eventually performing time-domain reflectometry tests on the actual produced boards to check it.

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