I have a CPLD XC9536XL-10VQG44C. On this CPLD I have one input "INPUT_4", one clock at 4MHz "clock" and 2 outputs "OUTPUT4_1" and "OUTPUT4_2", I also have 1 LED to drive that takes the same value than the input.
What I want to do is:
- When INPUT_4 goes high, turn OUTPUT4_1 high and OUTPUT4_2 low for 50ms then put them both back to low.
- When INPUT_4 goes low, turn OUTPUT4_1 as low and OUTPUT4_2 high for 50ms then put them both back to low.
So what I wanted to do was look for the input, and as soon as there is a change on it, do the corresponding change on the output and starting counting the 100ms. When the 50ms is finished, put them back low.
I appreciate that it is probably easier to do with a microcontroller but I cannot change the hardware.
For that I wrote that vhdl:
entity test_vhdl is Port ( Input_4 : in STD_LOGIC; Output4_1 : out STD_LOGIC; Output4_2 : out STD_LOGIC; LED_4 : out STD_LOGIC; Clock : in STD_LOGIC); --4MHz end test_vhdl; architecture Behavioral of test_vhdl is constant overflow : natural := 200000; --50ms pulse with a 4MHz frequency signal COUNTER_4 : natural range 0 to overflow; begin LED_4<=Input_4; output4: process(Input_4, Clock) is begin if rising_edge(Input_4)then Output4_1 <= '1'; Output4_2 <= '0'; COUNTER_4 <= 1; elsif falling_edge(Input_4) then Output4_1 <= '0'; Output4_2 <= '1'; COUNTER_4 <= 1; end if; else if rising_edge(Clock) then if COUNTER_4 /= 0 then COUNTER_4 <= COUNTER_4 + 1; if COUNTER_4 = overflow-1 then Output4_1 <= '0'; Output4_2 <= '0'; COUNTER_4 <= 0; end if; end if; end if; end if; end process output4; end Behavioral;
I simulated it and it works fine. But when I try to synthesize it I get the error:
Signal Output4_1 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
Maybe it comes from the fact that I check the rising edge of two different signals in the same process. I am still in the learning curve of VHDL, how can I resolve this problem or is there a better way of doing what I need to?