For low power design, clock enables can be used to turn off a block, thus reducing dynamic power. For example, if raw ADC data is being obtained and not FFT processed data, then that FFT module could be shut down using the clock enable.
My question is this:
- Does anyone have any resources (papers, white papers, app notes) that discuss separate block resets, where those resets are (a) secondary to the global reset and (b) are tied to a uProc's register map? Is this even good design practice?
- The design intent would be for run-time debug. Let's say we have a FIFO filled with data that is being transferred to uProc working memory via DMA. Now, if the DMA engine flags up that it has an issue, it would be useful to reset the DMA engine separately to the FIFO. Obviously global reset would reset everything including the FIFO and the uProc, meaning the data and processor status that was obtained during the fault is lost.
- For a uProc controlled FPGA design (SoC), there may be SPI/I2C peripherals, there may be DMA engines, memory banks, Ethernet controllers, DSP IP cores etc. If there was an issue with an SPI controller for example, I want to be able to reset this without a full global reset.
Has anyone seen any white papers or application notes for this strategy?