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I need to constrain a plane from shorting to the annular rings of a number of vias.

The dialog found at Rules and Constraints -> Design Rules -> Plane -> Power Plane Clearance allows me to enforce a clearance from a via, but that clearance appears to be reckoned from the hole diameter and not from the diameter of the annular ring.

The following two screen shots show the effect of an adjustment to the Clearance parameter from 10 to 6; when clearance is set to 10, the actual clearance to the annular ring is only 5 mils:

When clearance is set to 10, the actual clearance to the annular ring is only 5 mils

But when clearance is decreased to 1, the plane nearly shorts against the annular ring with only 1 mil of clearance:

When clearance is decreased to 1, the plane nearly shorts against the annular ring with only 1 mil of clearance

If every via shared the same annular ring diameter of 10 mils, for example, it would be possible to generate a single rule to give the desired clearance by simply adding 10 mils to the desired clearance. However, some vias have larger hole diameters and annular rings; a rule that fit the smaller vias would short the plane against the larger vias, and a rule that fit the larger vias would leave larger clearances than desired around the small ones.

One way to accommodate varied via sizes would be to add all vias to a class based on their size, then add a compensated rule to target each class. However, I'd like to avoid manually tagging thousands of objects into classes, and this work seems superfluous since Altium already knows the size of each object.

Is there a more succinct way to specify a uniform plane clearance from the annular ring of every via?

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    \$\begingroup\$ Are you sure Altium is placing annular rings (pads) on un-connected inner layers? Recent versions either don't do this or allow you to choose not do it. Your vendor will prefer it because it means drilling through less copper and not wearing out their drills as quickly. \$\endgroup\$ – The Photon Apr 25 at 16:26
  • \$\begingroup\$ Altium is not placing annular rings on unconnected power plane layers, therefore this is not as simple as it may seem. Also Altium does not have the concept of antipads in its pad/via library feature. So probably making a bunch of rules for the different via diameters is your best guess. \$\endgroup\$ – Manu3l0us Apr 26 at 9:36
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Power planes are a specific thing in Altium; just because you have a polygon pour connected to a power or ground net doesn't make it a power plane. What you'll want to do instead is set a regular clearance rule rather than a power plane clearance rule.

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  • \$\begingroup\$ The layer shown above is a power plane, not a pour. \$\endgroup\$ – Joel Apr 29 at 14:37
  • \$\begingroup\$ It looks like your looking at an inner layer in single view, is that correct? If so, what does your via stack look like? It looks to me like you don't have an annular ring on the inner layers, therefore the plane clearance would correctly be based on the distance to the edge of the hole. \$\endgroup\$ – A.Mac Apr 29 at 18:17
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We worked around inadequate constraints for power planes by implementing the layer as a pour instead. Pours are subject to the more comprehensive constraints that apply to polygons (see Rules and Constraints -> Design Rules -> Electrical-> Clearance -> Clearance). This constraint matrix allows you to specify a distance from a poly to other object types including vias, fills, etc.

The result of using a pour instead of a power plane is that we are able to specify a minimum distance that must be maintained between the annular ring of a via and our desired power plane.

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