You may want to tweak your approach regarding differential pair matching.
The question is not where "physically" on your board should you do the matching but where in your "system" can it be or should it be done. Let me try to explain.
The physical approach is what you mentioned: which layer, next to which part, serpentine or other matching pattern?
To answer all these, you have to understand the "system" you are building:
- Where is your transmitter / receiver? How can you place them so that you minimize the route length and matching complexity? How can you place them to avoid other "sensitive" area of your system?
- How crowded is your system in the area you are routing? Are there other high-speed devices near-by? Is there an RF or analog area to avoid? Which layers should allocate to each device? Does this high-speed route have special requirements?
Let's assume you have the placement done. The ideal routing solution is straight from transmitter to receiver using outer layer (no layer switch). Where should the matching be done: closer to transmitter, closer to receiver, in the middle?
My approach would be, where should you allocate space for the routing and matching of my differential pairs to keep clear from other routes for other devices? Examples: Will there be another high-speed devices needing routing/matching space near the transmitter? Are there any sensitive circuit near the receiver?
Now let's assume you have to switch layers and you wonder which layers to use. Is there another device requiring N signal layers of single high-speed routing near-by? Try to avoid these layers and route/match your pairs elsewhere.
Do you have to split pairs on different layers? Same thing here, just think of your overall system routing strategy and decide which layers to use and space to allocate for your matching.
Concerning the matching pattern, it also depends how much space your system allows you to allocate. You can do large zig-zagging if you have the space when the rest of your board routing is done. If the area is constrained, use tight serpentine where you have room.
When it comes to intra-pair length matching, you have to take into account that you are routing "differential" pair and you'll loose benefit of common-mode noise rejection if the signals inside your pair are completely un-phased. I would recommend (for SI and EMI) to try to keep them phased at all time, meaning if one signal in the pair gets shorter as you take a turn, try to re-match it immediately after.
Regarding signal integrity, you will find a lot of documentation online for best practices for differential high-speed routing (ground return vias, like you have, are among them). For EMI, well you are in luck with differential pairs are they are more forgiving than single-ended traces and if you keep signal length inside pairs relatively well matched, their electric fields cancel out and you won't see a thing on your spectrum analyzer.
One last thing which you may already know, in synchronous bus like MIPI, the matching pair reference is the clock. 50 micron matching between all the data pairs means nothing is the clock pair is 100mm shorter/longer (look-up "hold" and "setup" time terms). So make sure to fix you clock pair route before matching all data pairs ;)