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I'm currently busy routing a high speed design containing MIPI signals @ 2,5Gbit / lane to a connector on an 8 layer board. As MIPI also contains a clock pair, it is advisable to match the length between pairs as best as possible.

I've come pretty far so far with matching <0,05mm, but I'm wondering what is the best option to extend the length of a trace, see below picture:

Differential pair length matching between pairs

Some information: Blue = layer 1 Green = layer 3 Purple = layer 6

Layer 2 and 7 are ground layers

Option 1 is extending the traces on the inner layer and running them back on top to the connector. To me, this seems like an excellent option, as it gives me maximum spacing towards other traces. However, I'm wondering how much of an influence the traces running back towards the connector exactly on top of the layer 3 traces has. It is a differential pair, and there is a ground/reference layer in between, so I would think this would allow only minimal crosstalk or other effects.

Option 2 is the traditional serpentine tracing. This would be my least preferred option, but I don't have much choice because I can't extend the traces behind the connector.

However, if option 2 is preferred for whatever reason, I could change the option 1 by retracting the traces back towards the connector as much as possible, and add serpentine tracing on layer 3.

So my question, which of these 2 options would give best signal integrity and/or EMI compatibility?

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    \$\begingroup\$ At the 0.05 mm length, which is 50 microns, I think you are done with the matching. \$\endgroup\$ – analogsystemsrf Apr 26 '19 at 14:18
  • \$\begingroup\$ Yes, I'm done with matching, but I'm trying to discuss which of the options I used to get this matching is better EMI/SI wise. \$\endgroup\$ – IceBlackz May 1 '19 at 7:03
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For a given diffpair, both options seem valid. However I suggest thinking of the extension behind the connectors as an extension of the potential coupling surface. Just imagine it like a flattened coil.

Therefore I would strongly vote for option 2.

In addition option 2 minimizes the required space for the diffpair. As I usually try to keep them separated from other circuits, option 2 further leaves you with more free space for other parts of the system.

If you even need to match below 0.05mm length is another question, as you have to check the rise time of your bus.

A general rule is to keep the net length on a given layer as equal as you can within a bus of diffpairs as I think you are dealing with.

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  • \$\begingroup\$ Welcome to the site :-) (a) As explained here, you must disclose when you link to your own website. Failure to do that could result in various sanctions. This site gets many Spam attempts, including planting links to PCB manufacturers (for example). So to avoid future problems for you, I recommend that you stick to the rules. (b) Please provide context for links, as mentioned here e.g. include a brief relevant quote from the page, to explain how the link is useful. Thanks :-) \$\endgroup\$ – SamGibson Apr 30 '19 at 17:22
  • \$\begingroup\$ P.S. It's unclear what you mean by a "PM" - Stack Exchange sites don't have the same "PM" functionality which is common on typical internet forums. It also goes against the spirit of Stack Exchange, where questions are posted (and, more importantly, the answers are written) and can be read by everyone. PMs (obviously) don't have that benefit to others. Therefore I recommend you reconsider that part of your answer. Thanks :-) \$\endgroup\$ – SamGibson Apr 30 '19 at 17:30
  • \$\begingroup\$ Thanks for your answer Nocturn. I agree with the idea of the coupling effect, however, there is a ground layer in between. My baseless intuition says this will cancel out at least some of the coupling, and because I don't need the space behind the connector anyway, it makes a better option. The serpentine routing would potentially be seen as a straight line for high speed signals as suggested in this topic: electronics.stackexchange.com/a/145393/220495 \$\endgroup\$ – IceBlackz May 1 '19 at 7:07
  • \$\begingroup\$ @SamGibson: Thanks for pointing out the special aspects of Stack exchange. Especially due to the link, I tried to avoid the idea of advertising so I skipped naming the page or company. Cheers :) \$\endgroup\$ – Nocturn May 1 '19 at 18:09
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    \$\begingroup\$ @Nocturn - Thanks for the reply. However: "I tried to avoid the idea of advertising so I skipped naming the page or company." Writers are required to disclose when they are promoting anything (including themselves or their company) as in my first link previously - just "skipping" naming a link to your company could be considered even worse i.e. some people may consider it deliberate deception! I have read the link, and IMHO it doesn't specifically answer the original question. So, to prevent you being accused of spamming, I've edited your answer to remove it. \$\endgroup\$ – SamGibson May 1 '19 at 18:31
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You may want to tweak your approach regarding differential pair matching. The question is not where "physically" on your board should you do the matching but where in your "system" can it be or should it be done. Let me try to explain.

The physical approach is what you mentioned: which layer, next to which part, serpentine or other matching pattern?

To answer all these, you have to understand the "system" you are building:

  • Where is your transmitter / receiver? How can you place them so that you minimize the route length and matching complexity? How can you place them to avoid other "sensitive" area of your system?
  • How crowded is your system in the area you are routing? Are there other high-speed devices near-by? Is there an RF or analog area to avoid? Which layers should allocate to each device? Does this high-speed route have special requirements?

Let's assume you have the placement done. The ideal routing solution is straight from transmitter to receiver using outer layer (no layer switch). Where should the matching be done: closer to transmitter, closer to receiver, in the middle? My approach would be, where should you allocate space for the routing and matching of my differential pairs to keep clear from other routes for other devices? Examples: Will there be another high-speed devices needing routing/matching space near the transmitter? Are there any sensitive circuit near the receiver?

Now let's assume you have to switch layers and you wonder which layers to use. Is there another device requiring N signal layers of single high-speed routing near-by? Try to avoid these layers and route/match your pairs elsewhere. Do you have to split pairs on different layers? Same thing here, just think of your overall system routing strategy and decide which layers to use and space to allocate for your matching.

Concerning the matching pattern, it also depends how much space your system allows you to allocate. You can do large zig-zagging if you have the space when the rest of your board routing is done. If the area is constrained, use tight serpentine where you have room.

When it comes to intra-pair length matching, you have to take into account that you are routing "differential" pair and you'll loose benefit of common-mode noise rejection if the signals inside your pair are completely un-phased. I would recommend (for SI and EMI) to try to keep them phased at all time, meaning if one signal in the pair gets shorter as you take a turn, try to re-match it immediately after.

Regarding signal integrity, you will find a lot of documentation online for best practices for differential high-speed routing (ground return vias, like you have, are among them). For EMI, well you are in luck with differential pairs are they are more forgiving than single-ended traces and if you keep signal length inside pairs relatively well matched, their electric fields cancel out and you won't see a thing on your spectrum analyzer.

One last thing which you may already know, in synchronous bus like MIPI, the matching pair reference is the clock. 50 micron matching between all the data pairs means nothing is the clock pair is 100mm shorter/longer (look-up "hold" and "setup" time terms). So make sure to fix you clock pair route before matching all data pairs ;)

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