Initial Note
The highest priority input is RESET. If low, the FF is actively reset. But you have that tied high. So RESET isn't active.
1st Schematic Results
The next highest priority input is TRIG. But only if it is low (below it's \$\frac13\$\$^\text{rd}\$ threshold.) If low, it actively sets the FF. If it is above that threshold, it isn't supposed to take priority and instead the FF is left either in its prior state or else, if THRES is high (above it's \$\frac23\$\$^\text{rd}\$ threshold) then the FF will be actively reset.
In your first schematic, the simulator will first find the DC steady-state conditions (unless you use UIC.) And this means that your RC tied to DISCH and THRES will immediately start out at \$V_\text{CC}\$. So this means THRES is high and will attempt to actively reset the output. But note that THRES is the lowest-priority in this regard. So when your input signal to TRIG goes low, it will take over as higher priority and will actively set the output despite THRES "suggesting" a reset. (TRIG takes priority over THRES.) You can see that dominance in your output, readily.
Your TRIG starts out high in your first simulation (the red trace, I believe.) So TRIG isn't taking priority. Instead, THRES is allowed to take over and therefore the FF is reset (note that at first the green trace is low) and DISCH is inactive (leaving the RC in the initial DC steady state condition.)
However, when TRIG goes low, it takes over (higher priority) and therefore sets the FF (green trace goes immediately high) and also causes DISCH to become active and discharge the capacitor. Discharging the capacitor means that now THRES is low (and therefore now inactive.)
When TRIG goes high again, it no longer asserts its higher priority, leaving that to THRES. But THRES is still too low (the capacitor isn't yet charged enough), so it also cannot assert its lower priority, either. This leaves the FF where it was last at (high.) So the output continues to be high for a little while, during which the resistor charges the capacitor upwards. Eventually, as you can see, THRES does reach the point where it becomes active and asserts a reset to the FF causing the output to go low.
But shortly after, your TRIG input goes low and actively asserts its dominance causing the FF to be set and go back high. Which you observe.
This repeats and completely explains the first simulation results.
Here's what I get in simulation:
The dark blue trace is the voltage on the capacitor that's part of the RC timing element. You can see that it does indeed rise to \$\frac23\$\$^\text{rd}\$ of \$V_\text{CC}\$ before the next change at the output happens. The other two traces are what you plotted, I believe. The above output traces demonstrate the discussion above is accurate.
2nd Results
Assuming your new schematic (except that I refused to use \$100\:\Omega\$ and used \$1\:\text{k}\Omega\$ in the collector of the BJT), the simulator will again first find the DC steady-state conditions. So the RC element tied to DISCH and THRES will immediately start out at \$V_\text{CC}\$, again. THRES is high and will attempt to actively reset the output. But you've inverted TRIG, which now starts out low (because your input is high and causing the BJT to be actively pulling TRIG low.) So TRIG takes priority over THRESH and sets the FF. (DISCH is therefore inactive, so this leaves the capacitor at the fully charged DC steady state condition it started out at.) The output should be high.
When your input goes low, the BJT isn't active and the resistor pulls TRIG high and therefore inactive. Since the capacitor is still fully charged at this point, THRES can now take priority and it causes the output to be reset. The output should now be low and DISCH will now actively discharge the capacitor. As the capacitor voltage rapidly declines, THRES becomes inactive. But the FF state remains unchanged since TRIG is still inactive. So the discharge of the capacitor is allowed to fully complete and the output remains low for this period.
So far, and only so far, this matches your 2nd output.
When your input returns high, the TRIG goes low and takes priority forcing the FF to be set and the output to go high. DISCH becomes inactive and allows the capacitor to start charging. At first, THRES is inactive. But as the capacitor charges up THRES may become active (depending on the RC time constant and your driving input rate.) However, none of this matters because TRIG doesn't have priority. So for the entire time that TRIG is active low (while the input is high), the output will remain set. But the capacitor will continue to charge, too.
Now the behavior becomes more nuanced.
- If the RC time constant is such that the capacitor can charge sufficiently that TRIG becomes active before your input changes to low again, causing TRIG to go high and inactive, then THRES will reset the FF as soon as your input changes because TRIG is inactive and THRES can take over. So then you'd expect the output to immediately go low.
- If, however, the RC time constant is such that the capacitor cannot charge sufficiently that TRIG becomes active before your input changes to low again, then THRES will not yet be active and so the FF will remain in its prior state (set) for a while. In this case, you would NOT expect the output to go immediately low. Instead, you'd expect the output to go low once the capacitor charges up enough to cause THRES to become active. (Assuming this happens fast enough -- before the next change of TRIG, you will see a stretched high at the output followed by a short low.)
Since your second output results are consistent with condition (1) above, I believe your RC time constant is too short in the second output case. I can't explain it any other way.
Before you insist otherwise, here's what I get in simulation using your schematic (with the above mentioned modification to the collector resistor) when I keep the same values for the RC timing element (\$R=47\:\text{k}\Omega\$ and \$C=10\:\mu\text{F}\$):
I'm sure you note that this is NOT at all what you show in your simulation (except for the first \$\frac23\$\$^\text{rd}\$ second, or so.) But it is entirely consistent with what I wrote above and for case #2, which should be the results you see if your schematic is accurate and your simulator and models are performing correctly.
Here's what I get, though, with \$R=47\:\text{k}\Omega\$ and \$C=1\:\mu\text{F}\$ (reducing the time sufficiently that it can meet case #1 above):
Now, that does actually reflect what you show in your simulation. The datasheets I've read for the 555 are pretty clear on the descriptions and logic I applied above. So, from this I conclude that you must be in case #1, somehow, in your second schematic. I can read your second schematic and I can see that it asserts there is not the difference I say must be present. But things are what they are and I can't change that. And my simulator generated outputs also support my conclusions, as well.
