I'm trying to incorporate 2 16-bit ADCs into my DAS design, which will interface with an MCU which only has 1 available QSPI. The ADCs have a 16-bit parallel output, but the MCU only has a single 8-bit parallel interface, so I'm forced to use the serial interface capability of the ADCs. To realise the full throughput of the ADC (1Msps), a dual data line SPI needs to be used, as a standard single data line SPI only supports reduced throughput.
As such, I'm wondering whether I can share the QSPI clock between both ADCs, then connect 2 of the QSPI data lines to ADC1 and the other 2 data lines to ADC2, then perform the data rearranging once received by the MCU. Writing to the ADC registers could be achieved in much the same way.
Does this sound feasible at all? Obviously layout and length/capacitance matching between the shared clock and data lines would be quite important, but I wanted to understand whether this idea has any legitimacy whatsoever before continuing down this path any further.