I'm trying to incorporate 2 16-bit ADCs into my DAS design, which will interface with an MCU which only has 1 available QSPI. The ADCs have a 16-bit parallel output, but the MCU only has a single 8-bit parallel interface, so I'm forced to use the serial interface capability of the ADCs. To realise the full throughput of the ADC (1Msps), a dual data line SPI needs to be used, as a standard single data line SPI only supports reduced throughput.

As such, I'm wondering whether I can share the QSPI clock between both ADCs, then connect 2 of the QSPI data lines to ADC1 and the other 2 data lines to ADC2, then perform the data rearranging once received by the MCU. Writing to the ADC registers could be achieved in much the same way.

Does this sound feasible at all? Obviously layout and length/capacitance matching between the shared clock and data lines would be quite important, but I wanted to understand whether this idea has any legitimacy whatsoever before continuing down this path any further.

The ADCs I'm looking to use are the AD7616 and the MCU is the ATSAME70Q21.

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    \$\begingroup\$ Let’s know what ADC and what microprocessor you’re using so we can better understand the details., \$\endgroup\$ – joribama Apr 28 '19 at 5:29
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    \$\begingroup\$ The normal procedure for this, is to take the datasheets of the two chips and compare the interface timing values, giving attention to set-up and hold time and voltage levels. \$\endgroup\$ – Oldfart Apr 28 '19 at 6:39
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    \$\begingroup\$ After spending a few minutes looking at the data sheets, I see a few problems with your proposed approach. The QSPI interface was really designed to be used with flash memory and I’m not really sure you can repurpose it for your use. When all 4 lines are used, the QSPI lines are bidirectional, while the ADC lines are unidirectional, with 1 input and 2 outputs per IC. You would need two extra lines to connect to the SDIs of the ADCs. If you really need the maximum sampling rate, you may consider designing some glue logic with an FPGA or CPLD in between. \$\endgroup\$ – joribama Apr 28 '19 at 6:51
  • \$\begingroup\$ That's actually the sticking point I've just been trying to worth through as well. I don't mind adding an FPGA in between if it'll allow full throughput on both ADCs, I'll have a look around at some options now, thanks! \$\endgroup\$ – jars121 Apr 28 '19 at 6:52
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    \$\begingroup\$ @jars121 - most likely there is no way to guarantee synchronization between two independent SPI modules within the same MCU. Take a look at the manufacturer documentation. It sounds like a long shot to me, though. \$\endgroup\$ – joribama Apr 28 '19 at 19:50

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