I'm working on a project in magic VLSI design tool and Ive been able to create a working D flip flop and simulated it correctly in the IRSIM. The end goal was to create a counter with D flip flops. Once I put the D flip flops into feedback they seem to break the simulator and refuses to act as they should in a normal Qnot to D feedback path. Is there something in IRSIM that I'm missing? I included my feed back testing with Qnot into D and forced a logic 1 into D and removed it and it oscillates, but doesnt change Qcurrent ever. logic from D FF

logic from D FF

Testing Qnot feedback into D


Don't try to change the data input and the clock at the same time. You are violating the setup and/or hold time of your latch. Try changing the clock value about half-way between edges of the data input.

By the way, what you have is a level-sensitive bistable element, which I refer to as a latch. I reserve the word "flip-flop" for edge-sensitive elements.

  • \$\begingroup\$ I added a set and reset and now it works correctly once I seed it with a 1 and remove it. Thanks \$\endgroup\$ – Jm4u Apr 28 at 19:51
  • \$\begingroup\$ link \$\endgroup\$ – Jm4u Apr 28 at 20:00

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