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I am trying to understand how the below CMOS transistor schematic has approximate equal rise and fall times (resistance pull up equal to resistance pull down)

Below is the schematic:

enter image description here

I notice that there are two different paths in the pull up network: - width 4 in series with width 5 (resistance pull up = 2*(1/4 + 1/6) = 0.83 - and 3 transistors of width 6 all in series. (resistance pull up = 2*(1/6 + 1/6 + 1/6) = 1

And for the pull down network:

  • two transistors in series, both width two: resistance pull down = 1/2 + 1/2 = 1.
  • Again, two transistors in series, both width two: resistance pull down = 1/2 + 1/2 = 1.
  • transistor of width 1: resistance pull down = 1

I then found the parallel combination of these:

Ie. for the pull up network, I simply calculated 0.83 in parallel with 1, to get: 0.45

And same for the pull-down network, I calculated 1 in parallel in 1 in parallel with 1 to get: 1/3 = 0.33

Is this correct? I appreciate any help.

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  • \$\begingroup\$ use some PWL inputs (one per each of your logic inputs) to evaluate each of the unique pullup and pulldown paths, against 0.1pF loads. What do you see? \$\endgroup\$ – analogsystemsrf Apr 28 at 23:40
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They are optimizing the circuit for 'worst case' delays.We need to have nearly equal worst case delays in both pull-up and pull-down networks.

Also you may know that both rising and falling delay varies with varies with various inputs.Ideally we aren't concerned about the transistors in parallel as that would not cause the largest delay.

In pull-up network, the worst case delay would be when B=1,A=C=D=0. Which is where we see three PMOS(mobility nearly half that of nmos) in series.

In pull-down network, the worst case delay would be when either A=1,B=C=D=0 or A=0,B=C=D=1. Which is where we see equivalent to one NMOS(size 1) connected to ground.

Hope this helps!

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