I am trying to understand how the below CMOS transistor schematic has approximate equal rise and fall times (resistance pull up equal to resistance pull down)
Below is the schematic:
I notice that there are two different paths in the pull up network: - width 4 in series with width 5 (resistance pull up = 2*(1/4 + 1/6) = 0.83 - and 3 transistors of width 6 all in series. (resistance pull up = 2*(1/6 + 1/6 + 1/6) = 1
And for the pull down network:
- two transistors in series, both width two: resistance pull down = 1/2 + 1/2 = 1.
- Again, two transistors in series, both width two: resistance pull down = 1/2 + 1/2 = 1.
- transistor of width 1: resistance pull down = 1
I then found the parallel combination of these:
Ie. for the pull up network, I simply calculated 0.83 in parallel with 1, to get: 0.45
And same for the pull-down network, I calculated 1 in parallel in 1 in parallel with 1 to get: 1/3 = 0.33
Is this correct? I appreciate any help.