Can someone shed some light on the rationale for the SPDIF coaxial input circuits in: (1) the DIR9001 evaluation board (see schematics, page 7), and (2) in this Application Note from ST (see Figure 10 on page 12). They both use 74xx logic gates but put feedback resistors (as if it was an analog amplifier --- read: being used as an analog-signal amplifier) and even more puzzling, put DC-blocking capacitors at the input.

Additional question: if I want to add an isolation transformer (a 1:1 pulse transformer), do I need to change anything (for now, tentatively, I'm going with the two-stage circuit from Figure 10 of ST's application note). I assume that I need to add an additional DC-blocking capacitor at the primary of the transformer, and place the 75-ohm termination resistor on the secondary of the transformer --- BTW, I'm planning to use the Murata DA103J.   Would I need to change anything w.r.t. the circuits mentioned above?

EDIT: This is my tentative circuit --- are you suggesting that I do not need and could/should remove C3? enter image description here


1 Answer 1


The logic gates have a "U" in their name, which stands for "unbuffered".

The SN74LVC1GU04 datasheet says:

8.3.6 Unbuffered Logic

A standard CMOS logic function typically consists of at least three stages: the input inverter, the logic function, and the output inverter. Some devices have multiple stages at the input or output for various reasons. An unbuffered CMOS logic function eliminates the extra input and output stages; the device only contains the required logic function which is directly driven from the inputs and directly drives the outputs.

The unbuffered inverter is commonly used in oscillator circuits because it is less sensitive to parameter changes in the oscillator circuit due to having lower total gain than a buffered equivalent. To learn more about how to use an unbuffered inverter in an oscillator circuit, see Use of the CMOS Unbuffered Inverter in Oscillator Circuits.

In an oscillator circuit, or an S/PDIF input circuit, the input signal typically does not have logic voltage levels. The DC-blocking capacitor makes the circuit independent from whatever signal level the S/PDIF sender uses; the feedback resistor then biases the inverter in its linear region, near the switching threshold.

You do not need a DC-blocking capacitor after the transformer only if the transformer's output signal is not suitable for the following circuit. This would be the case for a logic gate, which does not support negative voltages.

  • \$\begingroup\$ Thanks @CL. I couldn't really understand what you mean in the last paragraph; in any case, see my edit above --- I added the diagram of my tentative input circuit. The 74LVC2GU04 datasheet has a footnote in the Absolute Maximum Ratings: "The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed", specifying that input voltage should be > ‒0.5V; however, it specifies an "Input clamping current", which can go up to 50mA. The 220-ohm resistor at the input should ensure a current limit. \$\endgroup\$
    – Cal-linux
    Apr 30, 2019 at 0:25
  • \$\begingroup\$ Actually, re-reading your answer, I think I should still leave C3? The output of the transformer should have zero DC voltage, but then, the input of the first NOT gate should be biased around some positive value? (likely, something between Vdd / 3 and 2Vdd / 3?) \$\endgroup\$
    – Cal-linux
    Apr 30, 2019 at 0:28

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