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In my pcb design I have 2 triangular voltage signals with the following specs:

  • Peak voltage = 300V
  • Rise and fall time= 7us
  • Freq=25kHz
  • (assume a constant current of 0.5A)

Because of the limited space available, I need to trace these signals on top of each other.

I am trying to get away with a 2 layer PCB board with a standard thickness of 1.6 mm.

My Question:

I am concerned about the crosstalk between the 2 traces due to capacitive coupling.

My attempt at an estimation:

  • C= (eo.er.L.w)/d
  • L=50 mm
  • w=0.6 mm (trace thikness)
  • er=4 (dielectric constant PCB)

Thus with these values I arrive at c=0.7 pF

Then with Ic= C*dv/dt= the induced current is 50 uA. This seems a very low current which would bring me to the conclusion that I can neglect this coupling.

But intuitively, I feel that I am missing something.

Or is the analysis good enough?

EDIT: (based on the answer by @Neil_uk) The two traces are going to 2 their loads which are capacitors. Hence the current is constant for linear slope. Thus I made the assumption that the inductive coupling could be neglected.

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    \$\begingroup\$ Capacity calculation seems reasonable to me. What is the phase relation between the signals/what is the highest possible voltage difference? Because this is a property which influences the dv in the current calculation. What PCB tool are you using? Because many modern EDA support the simulation of such properties. Do you use certain guideline(s) as 300V/0.5A is serious buisness. \$\endgroup\$ Commented Apr 29, 2019 at 9:36
  • \$\begingroup\$ Two signals are in phase, the maximum voltage is 300V i.e. when one output is zero and the other is max. And no, I use general guide lines and my pcb tool is altium. Note that the 300V 0.5 A is not constant. \$\endgroup\$
    – Navaro
    Commented Apr 29, 2019 at 9:45
  • \$\begingroup\$ Then I would recommend to use the built in Signal Integrity Analyses of altium. \$\endgroup\$ Commented Apr 29, 2019 at 13:54
  • \$\begingroup\$ Current is constant, except at certain moments when it is changing very quickly. \$\endgroup\$
    – The Photon
    Commented Apr 29, 2019 at 16:48

1 Answer 1

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Assuming the geometry you've given, you've done the sums correctly to get to 0.7pF. However, that will be an underestimate for the true capacitance which will be dominated by fringeing fields, rather than parallel plate capacitance. Inflate your figure by a factor of 2 or 3, to get 2pF. That should be accurate enough for back-of-envelope work (until somebody cranks up a line solver and posts the correct figure). (edit - The correct figure is 1.6pF, using a microstrip calculator, half the result for half the substrate thickness /edit)

Given 0.7pF, I get 30uA for a dV/dt of 300v in 7uS. A triangular waveform of 25kHz doesn't have a 7uS rise/fall time, so I'm not sure what your waveshape is. 30uA is essentially the same as 50uA if we're on the back of an envelope.

Whether the resulting 100uA (assuming 2pF) between traces is too much depends on what else is going on in the circuit. It may be trivial in a power circuit, and a job-stopper in a measurement circuit, you don't say what yours is. If that 0.5A figure you give is a reference for what's relevant, then 100uA may be far enough below that to be negligible for your application.

There will also be inductive coupling between the traces, which could be a problem if one carries a rapidly varying current, and you're sensing the voltage across the other. You don't say whether your circuit has these features.

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  • \$\begingroup\$ I edited my answer : so the fringeing field increase the effective area? \$\endgroup\$
    – Navaro
    Commented Apr 29, 2019 at 9:28
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    \$\begingroup\$ @Navaro Yup, fringing field becomes a larger contribution to the total as the width decreases. Once the width/height becomes less than 1, the fringing contribution is larger than the parallel plate contribution. Find a microstrip calculator, I used this one, and play with some W/h ratios. \$\endgroup\$
    – Neil_UK
    Commented Apr 29, 2019 at 10:07

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