# Coupling PCB traces

In my pcb design I have 2 triangular voltage signals with the following specs:

• Peak voltage = 300V
• Rise and fall time= 7us
• Freq=25kHz
• (assume a constant current of 0.5A)

Because of the limited space available, I need to trace these signals on top of each other.

I am trying to get away with a 2 layer PCB board with a standard thickness of 1.6 mm.

My Question:

I am concerned about the crosstalk between the 2 traces due to capacitive coupling.

My attempt at an estimation:

• C= (eo.er.L.w)/d
• L=50 mm
• w=0.6 mm (trace thikness)
• er=4 (dielectric constant PCB)

Thus with these values I arrive at c=0.7 pF

Then with Ic= C*dv/dt= the induced current is 50 uA. This seems a very low current which would bring me to the conclusion that I can neglect this coupling.

But intuitively, I feel that I am missing something.

Or is the analysis good enough?

EDIT: (based on the answer by @Neil_uk) The two traces are going to 2 their loads which are capacitors. Hence the current is constant for linear slope. Thus I made the assumption that the inductive coupling could be neglected.

• Capacity calculation seems reasonable to me. What is the phase relation between the signals/what is the highest possible voltage difference? Because this is a property which influences the dv in the current calculation. What PCB tool are you using? Because many modern EDA support the simulation of such properties. Do you use certain guideline(s) as 300V/0.5A is serious buisness. Apr 29, 2019 at 9:36
• Two signals are in phase, the maximum voltage is 300V i.e. when one output is zero and the other is max. And no, I use general guide lines and my pcb tool is altium. Note that the 300V 0.5 A is not constant. Apr 29, 2019 at 9:45
• Then I would recommend to use the built in Signal Integrity Analyses of altium. Apr 29, 2019 at 13:54
• Current is constant, except at certain moments when it is changing very quickly. Apr 29, 2019 at 16:48