I want to know if my understanding of this state machine diagram is correct.

The input is connected to a toggle: 0001,1 <- This 1 represent toggling the input

Initially, when the circuit powers on, it is in state 00 and the input could either be 1 or 0.

If 1, 0001 displayed again and the input is toggled to 0. When the input is 0 there is a state transition which displays 0010, at this state there is no toggle bit so the input is still 0, this causes a transition to the next state again

Is my understanding correct? Thank you

enter image description here


State machines have an input that by convention isn't explicitly mentioned on the state diagram: the clock. In your case, it appears that what you call "the toggle button" is used to generate the clock.

This state machine has (according to the diagram) another input that you haven't mentioned, called Dir. This input and the current state determine what state the machine transitions to on each clock event.

This state machine has 5 outputs. Four outputs control the 4 LEDs. The 5th output probably controls some other logic that produces the Dir input. Seeing what text is attached to the arrow pointing in from the right side of your image snippet might make this more clear.

All the bits indicated below the line in each state bubble indicate outputs, not inputs.

The input is connected to a toggle: 0001,1 <- This 1 represent toggling the input

I would read it as a fifth output, not an input. Inputs should be marked along the lines, so you know what combination of inputs causes which transition.

Consider what you'd do if you had a more complex state machine with more than two possible transitions out of some of its states. Or with more than two transitions in to some of the states. You might even use a different set of inputs to get to state C from state A than you use to get to C from B. In that case putting the inputs needed to enter the state inside the state bubble would be very confusing.

  • \$\begingroup\$ A Moore state machine by definition is synchronous, so the clock is implied. DIR could be an external RS flip flop cleared by )) and set by 11, it does not have to be part of the internal state. \$\endgroup\$ – Jack Creasey Apr 29 at 16:11
  • \$\begingroup\$ @JackCreasey, Isn't "not explicitly mentioned" the same as "implied"? And where did I say Dir is part of the internal state? I said "some other logic" (meaning, not part of this SM) produces Dir; an RS flip flop is an example of something that could be used to implement that other logic. But my guess would be Dir is generated by a T-flip-flop since we only have one output bit from this SM to control it, and it goes high whenever we'd want to toggle Dir. \$\endgroup\$ – The Photon Apr 29 at 16:20
  • \$\begingroup\$ Just pointing out where I thought it needed to be. \$\endgroup\$ – Jack Creasey Apr 29 at 17:19
  • \$\begingroup\$ @JackCreasey, sorry, now I have no idea what you're trying to say. Where what needed to be? \$\endgroup\$ – The Photon Apr 29 at 17:30
  • \$\begingroup\$ I doubt DIR would be generated by a 'T' flip-flop since it is clocked. My comment was that Moore means it IS synchronous, there is no doubt. Not all state machines MUST be synchronous. To actually answer the Op's question you really need to see the whole question, especially the elements on the LHS and RHS. I'm sorry you seemed to take offence at my comment, none was implied. \$\endgroup\$ – Jack Creasey Apr 29 at 19:28

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