Variable frequency for sine wave in Verilog [duplicate]

This question is an exact duplicate of:

I am trying to implement 4 different frequencies at which sine wave is going to be simulated in testbench. I am using a counter to do so. However, it can not toggle clk_out in simulation window. Not sure where the error is.

Code:

module functionGenerator(Clk,data_out, reg0, clk_out);
//declare input and output
input Clk;
output [9:0] data_out;
output reg clk_out;
input [3:0] reg0;
reg [31:0] constantNumber;
reg [9:0] sine [0:99];
integer i;
reg [9:0] data_out;
reg [31:0] count;
//Initialize the sine rom with samples.
initial begin
i = 0;
clk_out = 0;

sine[0] = 0;        sine[1] = 10;        sine[2] = 20;        sine[3] = 29;        sine[4] = 39;
sine[5] = 48;       sine[6] = 58;        sine[7] = 67;        sine[8] = 75;        sine[9] = 84;
sine[10] = 92;      sine[11] = 100;      sine[12] = 107;      sine[13] = 114;      sine[14] = 120;
sine[15] = 126;     sine[16] = 132;      sine[17] = 137;      sine[18] = 141;      sine[19] = 145;
sine[20] = 149;     sine[21] = 151;      sine[22] = 153;      sine[23] = 155;      sine[24] = 156;
sine[25] = 156;

end

always @ (reg0)
begin
if(reg0 == 4'b0000)
constantNumber = 50;
else if(reg0 == 4'b0001)
constantNumber = 100;
else if(reg0 == 4'b0010)
constantNumber = 200;
else if(reg0 == 4'b0100)
constantNumber = 300;
else if(reg0 == 4'b1000)
constantNumber = 400;
else
constantNumber = 500;
end

always @ (posedge(Clk))
begin
if (count == constantNumber - 1)
begin
count <= 32'b0;
end
else
begin
count <= count + 1;
end
end

always @ (posedge(Clk))
begin
if (count == constantNumber - 1)
clk_out <= ~clk_out;
else
clk_out <= clk_out;
end

//At every change in clk_out state, output a sine wave sample.
always@ (clk_out)
begin
if ( i < 25 )
data_out = sine[i];
else if ( i < 50 )
data_out = sine[50 - i];
else if  ( i < 75 )
data_out = - sine[i - 50];
else
data_out = - sine[100 - i];
i = i+ 1;
if(i == 100)
i = 0;
end
endmodule


and Test bench:

module functionGeneratror_tb();

// Inputs
reg Clk;
reg reg0;
wire clk_out;
// Outputs
wire [9:0] data_out;

// Instantiate the Unit Under Test (UUT)
functionGenerator uut (
.Clk(Clk),
.data_out(data_out),
.reg0(reg0),
.clk_out(clk_out)

);

//Generate a clock with 10 ns clock period.
initial
begin
Clk = 0;
reg0 = 4'b0000;
end
always #5 Clk = ~Clk;

endmodule



marked as duplicate by Elliot Alderson, Dave Tweed♦Apr 29 at 17:30

This question was marked as an exact duplicate of an existing question.

• Exactly how does the simulation fail? If there are any errors or warnings in the console, copy them into your question. – Elliot Alderson Apr 29 at 17:03
• I edited the question. The simulation executes but the waveform is wrong. – RytisBe Apr 29 at 17:10
• In your code, you have a comment saying you want to do something on every positive edge of clk_out, but then the code does something on every edge, going either way. – The Photon Apr 29 at 17:12
• Yes sorry, i had it essentially checking each clk pos edge but now i want to do combinational logic. – RytisBe Apr 29 at 17:15
• As combinatorial logic, your code is equivalent to connecting a NOT gate between clk_out and itself, enabled whenever the count condition is met. You have no control over how many times clk_out toggles during the cycle of Clk when the count condition is met. – The Photon Apr 29 at 17:21

You never initialized clk_out, so the initial value is x.

Then you keep toggling clk_out, but since the simulator doesn't know the initial value, the value after toggling is still x.

You can resolve this by initializing clk_out, either in the declaration, in an initial block, or by defining a reset condition in the always block that controls it (which will work for synthesis but I'm not 100% sure it will work in simulation).

Also, I noticed another issue,

//At every positive edge of the clock, output a sine wave sample.
always@ (clk_out)


Your comment says you want to respond to positive edges, but your code says to respond to all edges.

The code is probably not synthesizable.

• I changed it already. It was sequential logic before, but combinational here is used instead. – RytisBe Apr 29 at 17:18