Is it because of segmentation? If yes, then how? I don't see any problem using any 16-bit memory.

  • \$\begingroup\$ A CISC (Complex Instruction Set Computer) with lots of instructions with various addressing modes to minimize memory used, when memory was expensive. 3+2 = 5, why use 16-memory locations, when the numbers fit in 8-bits. \$\endgroup\$ – StainlessSteelRat Apr 29 '19 at 19:26
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    \$\begingroup\$ unclear what you are asking. my 64 bit x86 deals with 8 bit memory as well as 64 bit arm. \$\endgroup\$ – old_timer Apr 29 '19 at 19:29
  • \$\begingroup\$ as well as most general purpose processors (some used 9 bit bytes, some other sizes, but in general support byte operations and addressing modes, some exceptions exist.). \$\endgroup\$ – old_timer Apr 29 '19 at 19:31
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    \$\begingroup\$ the 8086 has a 16 bit bus, the 8088 if that is what you meant to ask is 8 bit because at the time those were the cheap memories available...16 bit internal 8 bit external. the 8086 could handle 8 bit transfers, but could also do 16, if you could afford the memory. \$\endgroup\$ – old_timer Apr 29 '19 at 19:31
  • \$\begingroup\$ The 8086 just has a 16-bit data bus. If you don't need it, then you would not choose 8086. You would choose the 8088 which as an 8-bit data bus. \$\endgroup\$ – Justme Apr 29 '19 at 19:32

When the 8088/86 came out, 8 bit memories were the norm and affordable. To have a 16 bit bus you needed two parts, so it cost you more in some way, half sized parts but two of them or same size parts and two of them would be twice the cost. So the design allows for the 8088 to use 8 bit parts and do two bus transfers or the 8086 and is capable of one transfer.

External and internal are not related. Many/most of the instructions from the 8086 are present today where the busses are much wider. And from edge of the processor core to the now dram (then sram) goes through a number of busses and transfer size changes, etc. The dram can be implemented using x8, x16, x32 parts. Typically 72 bits wide on a full sized motherboard, sometimes 64, so if you have say 8 or 9 parts on one side of the dimm then they are 8 bit wide parts, if both sides populated with 8 or 9 still 8 bit wide parts, but two ranks. 4 or 5 parts on a side then x16, etc. Because of the nature of the number of busses, the external geometry then as now doesnt matter so long as it confirms to the bus interface that the memory is connected to. It doesnt define what the internals are in any way shape or form.

As new DDR tech comes out, DDR2, DDR3, DDR4, etc. you often find them starting with x8 parts being the most affordable, then x16 not long after and so on. density vs yield.

now phone memory lpddr4, etc those busses are like 16 bits wide and you just do more transfers per cache line than you would with a 64/72 bit wide bus. same instruction set inside, "byte addressable"

Kinda similar but the same house you live in could be a on a one way single lane road, a two way road, two way with a median, four lane, four lane with a median, could be strictly next to a big parking lot and not on a road, etc. Does not in any way affect the sheets on your bed or use of towels in the bathroom. The two things are not related, the overall system design is such that it tries to get affordable memory in quantity that is not horribly slow for the processor in question.

  • \$\begingroup\$ This is a response to a different question than the one actually asked \$\endgroup\$ – Chris Stratton Apr 29 '19 at 19:42
  • \$\begingroup\$ @ChrisStratton you figured out what the question is? \$\endgroup\$ – old_timer Apr 29 '19 at 19:49
  • \$\begingroup\$ The question we seem to be understanding, and this answer primarily deals with the why then and added info on why it still isnt relevant now. The why then was because of the price and availability of parts (as it is today). has nothing to do with segmentation or anything else, strictly price and availability of parts. \$\endgroup\$ – old_timer Apr 29 '19 at 19:52
  • \$\begingroup\$ I was thinking of some more technical but crisp answer actually...this one looks good, but it also brings out its history, availability etc. \$\endgroup\$ – Mathew Hayes Apr 29 '19 at 23:14
  • \$\begingroup\$ yeah, no magic there. sorry. \$\endgroup\$ – old_timer Apr 30 '19 at 15:03

The 8086 had a dual memory structure to allow for 16-bit rams or 8-bit rams. (The 8088 only had an 8-bit data bus and could only use 8-bit rams) If the 16-bit rams were used, it was divided up into two banks of 8 bits. 16-bits allowed for newer rams, 8-bits allowed the architecture to be somewhat compatible with other chips and older rams.

enter image description here Source: www.sbcecarni.org/sbadmin/admin/downloading/uploads/57887-8086-architecture.pdf

  • \$\begingroup\$ So you are saying that since diving into 2 memory banks and accessing them to generate the physical address is more feasible, it works in 8-bit form? \$\endgroup\$ – Mathew Hayes Apr 29 '19 at 23:12
  • \$\begingroup\$ It's more of a hassle actually, but it gave you options with hardware. \$\endgroup\$ – Voltage Spike Apr 30 '19 at 1:14

Many processors treat memory as byte-addressable, even if the physical data bus is much wider. This is because programmers find it useful to be able to manipulate data in 8-bit chunks.

This means that 16-bit memory attached to an 8086 needs to have the ability to write to only one byte at a time, controlled by the BHE and BLE signals. Newer members of the family have similar control signals.


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