# BJT astable multivibrator generate triangle wave In this circuit there is a bjt astable multivibrator. It generates a square wave. And according to the description, at the output of the opamp it generates a triangle wave from this square wave.

I've tried to implement this circuit in LTSpice. When I simulate output of the first circuit (astable multivibrator) looks fine. But if you look at the output of the opamp there are some glitches rather than triangle wave. What might be wrong with this circuit here.

Edit :

I changed the value of R6 resistor to 1000000 ohms but still output of the opamp doesn't look like a triangle wave. Edit2 : After playing around with potentiometer values,I should be able to see a waveform which looks like triangle at the output of opamp. But if I increase the simulation time from 100 milli seconds to 700 milli seconds I see DC 15 volts at the output of op amp. I don't know why this happens.

• Add a large cap in series with R5; and set the pot to zero. – analogsystemsrf Apr 30 '19 at 13:23
• When I add a large cap in series with R5 let's say 100u and set the pot to zero output of op amp hits -15 volts. – Erdem Apr 30 '19 at 13:44
• then WAIT for the initial charges to stabilize. With no DC current into the OPAMP, the final average output must be centered around zero volts, at least for 50% duty cycle from the oscillator. – analogsystemsrf Apr 30 '19 at 14:00

So the output of vibrator is a pulse which should be the input of the integrator as to gain the triangular waveform. In your simulation R6 =1 milliohm instead of 1 Mega.

You are basically shorting the integrating capacitor.

The correct symbol for megaohm = Meg in LT spice.

EDIT: As Bimpelrekkie mentioned, since you have a open-loop system your op- amp will drift.

The simulation below shows how you can charge and discharge the capacitor based on the output. How it works ?

So at t=0 , assumme output is zero and the output of the flip flop is zero. The input at summing amplifier has only the negative dc voltage, this causes a linear rise due to the integrating capacitor.

Once the (arbitrary) threshold of 7V is reached the Comparator U2 goes high and sets the Flip flop which has an output voltage of 2V. As a result, the voltage at the output of the summing amplifier jumps from -1V to (-1V + 2V) 1V, this causes the voltage to fall linearly. Once the voltage goes below 0.05 V, U3 goes high which resets the flip flop and the summing point jumps back to -1 and the cycle repeats.

Do not mind the simulation is not very neat , but gives a idea how you could approach the problem.

I see DC 15 volts at the output of op amp. I don't know why this happens

I do ;-)

This circuit has an essential flaw.

The integrator relies on the fact that the capacitor is charged and discharged with exactly the same amount of charge every time. It is an integrator so keeps adding / subtracting charge into C3.

That means that the square wave generator needs to generate a perfect 50% duty cycle square wave, which it cannot. That's why the potmeter U1 is there, to dial out any offsets.

However, that will not prevent any charge/discharge imbalance from adding up so the sawtooth voltage will eventually "drift" up or down. In your simulation the output drifts down as the charge/discharge imbalance accumulates.

This behavior is a consequence of the simplicity of this circuit. It does not monitor its output voltage to compensate for the drift.

To solve this use a circuit which decides when to start charging/discharging based on the value of the output voltage. The 555 timer chip works like that, it has a window comparator to keep the voltage across the timing capacitor between 2/3 Vdd and 1/3 Vdd. Of course the 555 isn't a proper sawtooth generator, it is just the principle I refer to. Needless to say, a "better" sawtooth generator is going to be a bit more complex.

Another alternative is to generate the sawtooth digitally using a DDS like the AD9833 on Ebay you can buy modules with this chip.

• An easy fix: in series with the 10k resistor, put in a blocking capacitor (10 uF would do). – Whit3rd Apr 30 '19 at 23:40
• @Whit3rd Unfortunately it is not as simple as that. The 10k resistor needs to be a resistor without a series cap. The input of the integrator is kept at a constant voltage (set by the potmeter, via opamp's feedback) so that there will be a square wave voltage across the 10 k resistor. That results in a square wave shaped current into the integrator. If you add a cap in series with the 10 k resistor then that cap will charge /discharge and the shape of the current will no longer be a proper square wave. Try it in a circuit simulator and see what happens! – Bimpelrekkie May 1 '19 at 6:51
• It's not ideal, but the current would be the same as in the 0.1uF feedback capacitor, so only one percent (of the tri wave amplitude) errors. – Whit3rd May 1 '19 at 10:22