I want to build a prototype device that manages to do the following:
Take a HDMI signal with at least 4k resolution at 60fps (for simplicity without DHCP for now,) change a few pixels (say a red circle in the center of the screen) and output the altered signal at 4k60fps and add less than 10ms of latency.
Price of the hardware matters, since I need to build a small batch of these devices (less than 200.)
The two viable options I see currently (please tell me if you see better options.)
A small desktop computer with a HDMI capture card plus a workstation graphics card that either supports GPUDirect (Nvidia) or DirectGMA (AMD.) However, these graphics cards are expensive (800$+) and I suspect even with GPUDirect/DirectGMA it will be difficult to add less than one frame (16.6ms) of latency going that route.
Some FPGA (which though?)
While I have done some small FPGA projects in the past, my know how is very shallow at that point, so what I'm looking for is the cheapest FPGA that can manage to decode a 4k60 HDMI stream and encode another.
From the information I gathered so far, I understand that:
The 'smallest' 4k60 HDMI signal is 4:2:0 chroma subsampling with 8bit depth per channel (http://community.cedia.net/blogs/david-meyer/2018/05/16/hdmi-data-rates-for-4k-hdr) which requires a 9.0 Gbps link speed
HDMI sends data over 4 TMDS channels (https://en.wikipedia.org/wiki/HDMI,) 3 for data, one for clock (I'm not sure whether that means I need at least 9.0/3 = 3.0Gbps speed per channel or whether I need at least 9.0/4 = 2.25Gbps per channel.)
What I wonder now is what the minimal hardware requirements in an FPGA are that I need to look for to get this done.
Looking at the Intel Cyclone V FPGAs, the more expensive GX and SX chips are advertised to have "3.1 and 6.1 Gps Transceivers" (anywhere between two and 12 of them), whereas the lower cost FPGAs do not have these transceivers - however, all of them (including the cheaper ones) also are indicated to have multiple "LVDS channels", which according to wikipedia is a differential signal (like TMDS) carrying 655Mbps (but apparently up to 3Gbps should be possible.)
Looking at Xilinx's Spartan 6 FPGA's they are advertised as having 3.2 Gbps "transceivers" in the more expensive LXT boards, and no transceivers at all in the cheaper LX boards.
My questions are now:
- Do I need these 3.x or 6.x Gbps transceivers to get this task done? If so, which ones and how many?
- Do FPGAs that are not advertised to have these 3.x/6.x Gbps transceivers have no transceivers at all, or are the ones they have simply slower?
- What are the minimum FPGA feature requirements for decoding and encoding 4k60 HDMI signal?
- Any idea on what sort of added latency I could expect if doing this through an FPGA?
- Are there more viable alternatives to FPGAs do to this?