I want to build a prototype device that manages to do the following:

Take a HDMI signal with at least 4k resolution at 60fps (for simplicity without DHCP for now,) change a few pixels (say a red circle in the center of the screen) and output the altered signal at 4k60fps and add less than 10ms of latency.

Price of the hardware matters, since I need to build a small batch of these devices (less than 200.)

The two viable options I see currently (please tell me if you see better options.)

  1. A small desktop computer with a HDMI capture card plus a workstation graphics card that either supports GPUDirect (Nvidia) or DirectGMA (AMD.) However, these graphics cards are expensive (800$+) and I suspect even with GPUDirect/DirectGMA it will be difficult to add less than one frame (16.6ms) of latency going that route.

  2. Some FPGA (which though?)

While I have done some small FPGA projects in the past, my know how is very shallow at that point, so what I'm looking for is the cheapest FPGA that can manage to decode a 4k60 HDMI stream and encode another.

From the information I gathered so far, I understand that:

What I wonder now is what the minimal hardware requirements in an FPGA are that I need to look for to get this done.

Looking at the Intel Cyclone V FPGAs, the more expensive GX and SX chips are advertised to have "3.1 and 6.1 Gps Transceivers" (anywhere between two and 12 of them), whereas the lower cost FPGAs do not have these transceivers - however, all of them (including the cheaper ones) also are indicated to have multiple "LVDS channels", which according to wikipedia is a differential signal (like TMDS) carrying 655Mbps (but apparently up to 3Gbps should be possible.)

Looking at Xilinx's Spartan 6 FPGA's they are advertised as having 3.2 Gbps "transceivers" in the more expensive LXT boards, and no transceivers at all in the cheaper LX boards.

My questions are now:

  • Do I need these 3.x or 6.x Gbps transceivers to get this task done? If so, which ones and how many?
  • Do FPGAs that are not advertised to have these 3.x/6.x Gbps transceivers have no transceivers at all, or are the ones they have simply slower?
  • What are the minimum FPGA feature requirements for decoding and encoding 4k60 HDMI signal?
  • Any idea on what sort of added latency I could expect if doing this through an FPGA?
  • Are there more viable alternatives to FPGAs do to this?

closed as off-topic by Leon Heller, Warren Hill, Elliot Alderson, Dave Tweed Apr 30 at 12:33

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  • \$\begingroup\$ Not an answer to everything you asked, but at least for some points. First of all what is the purpose of this, and second, not many sources will give 4k60 without HDCP. 4k60 4:2:0 is 9 Gbit signal so 3Gbit/channel. 3 deserializers for receiving and 3 serializers for transmitting. Also the clock input and clock output ports are necessary. Latency should be below 10ms unless you have a frame buffer. \$\endgroup\$ – Justme Apr 30 at 11:29
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    \$\begingroup\$ What you want is an NeTV, which is specifically designed for this: crowdsupply.com/alphamax/netv2 \$\endgroup\$ – pjc50 Apr 30 at 11:41
  • \$\begingroup\$ I did read about NeTV before and yes, this is basically what I'm looking for, but the NeTV device only supports up to 720p and NeTV2 (not yet out as it seems?) only up to 1080p \$\endgroup\$ – user1282931 Apr 30 at 14:32
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    \$\begingroup\$ 1. As Justme commented, the 3.1 Gbps transceivers should be sufficient, the 9Gbps link rate is divided by 3 data channels. 2. If transceivers are not explicitly called out there are none. Note MGT (multi gigabit transceivers are different than I/O serdes blocks on many normal FPGAs that top out at about 1-2Gbps (high end FPGAs). 3. An Artix 7 (Xilinx) Cyclone V (intel), or ECP3 (Lattice) would be your best bet for inexpensive FPGA chips. 4. It should be possible to do this with several lines of latency. 5. To meet the goal of sub frame <10ms latency FPGAs are the best option. \$\endgroup\$ – davidd Apr 30 at 16:45
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    \$\begingroup\$ Correction on #5: A chip like this might be exactly what you need: analog.com/en/products/adv7627.html#product-overview \$\endgroup\$ – davidd Apr 30 at 18:21

I think you are going about this all wrong. As it is obvious that you are just now entering this area of engineering the first step should be to do work to build a working model or prototype so that you can learn about the tools, algorithms, intellectual property (IP) development and open source IP. If you choose to go the FPGA route you should select a development platform that does not fetter your ability to achieve the end result.

Once you become well versed in the technology and have built a working model then you can begin to think about fitting that to the most cost effective solution. The algorithms that will need to be developed should be portable if you develop them in a hardware description language (HDL).

Make no mistake, the project you are talking about will not be an "easy task done over some weekend". This is going to be a huge opportunity to learn about technology and how to tune that knowledge into a working application.

  • \$\begingroup\$ You are right - but since I don't have enough knowledge, I would need to buy the most expensive FPGA I can find and see if I can get it done with that. I need a sane lower bound of what I need to get this done \$\endgroup\$ – user1282931 Apr 30 at 14:26

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